Method for compressing and decompressing image signals and apparatus for compressing and decompressing image signals

ABSTRACT

A method is provided for achieving high-speed 2 N -2 N  DCT and 2−2 N−1 −2 N  DCT in a miniaturized circuit. 
     An 8-8 DCT is performed by using multiplexers, registers, adding circuits, subtracting circuits, adding/subtracting circuits, fixed coefficient multiplying circuits, AND circuits or a like. A 2-4-8 DCT is performed by using a part of the circuit for performing the 8-8 DCT by switching operations of multiplexers, adding/subtracting circuits, fixed coefficient multiplying circuits, registers between operations for the 8-8 DCT and for the 2-4-8 DCT.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for compressing of imagesignals and decompressing of image signals and to an apparatus toimplement of image signals compressing of image signals anddecompressing of image signals.

The present application claims the Convention Priority of JapanesePatent Application No. Hei11-326188 filed on Nov. 16, 1999, which ishereby incorporated by reference.

2. Description of the Related Art

Conventionally, when a digitized image is transmitted, since an amountof image information is enormous, the image information is compressedprior to its transmission. As one of methods for compressing imageinformation, international standard coding systems called MPEG (MovingPicture Experts Group) and JPEG (Joint Photographic Experts Group) areknown. In the international standard coding systems, input image data iscompressed by DCT (Discrete Cosine Transformation) and compressed imagedata is returned to its original image data by IDCT (Inverse DiscreteCosine Transformation).

The DCT used in the international standard coding systems is performedin accordance with the following equation (17) provided for inInternational Standard (STD•IEC 61834-2-ENGL 1, 998) 8-8 DTC, whichprescribes the international standard coding systems. The IDCT used inthe international standard coding systems is performed in accordancewith the following equation (18) provided for in the InternationalStandard (STD•IEC 61834-2-ENGL 1, 998) 8-8 IDCT, which also prescribesthe international standard coding systems. $\begin{matrix}{{{{F\left( {h,v} \right)} = {{C(v)}{C(h)}{\sum\limits_{y = 0}^{7}{\sum\limits_{x = 0}^{7}\quad {\left\{ {{f\left( {x,y} \right)}\cos \quad \alpha} \right\} \cos \quad \beta}}}}}{where}{{{C(h)} = {\frac{1}{2\sqrt{2}}\quad \left( {h = 0} \right)}},\quad {{C(h)} = {\frac{1}{2}\quad \left( {{h = 1},2,\ldots \quad,7} \right)}}}{{C(v)} = {\frac{1}{2\sqrt{2}}\quad \left( {v = 0} \right)}},\quad {{C(v)} = {\frac{1}{2}\quad \left( {{v = 1},2,\ldots \quad,7} \right)}}}{{\alpha \equiv \frac{\pi \quad {v\left( {{2y} + 1} \right)}}{16}},\quad {\beta \equiv \frac{\pi \quad {h\left( {{2x} + 1} \right)}}{16}}}} & {\quad (17)} \\{{{f\left( {x,y} \right)} = {\sum\limits_{v = 0}^{7}{\sum\limits_{h = 0}^{7}\quad \left\{ {{C(v)}{C(h)}{F\left( {h,v} \right)}\cos \quad {\alpha \cdot \cos}\quad \beta} \right\}}}}{where}{{{{C(h)} = {\frac{1}{2\sqrt{2}}\quad \left( {h = 0} \right)}},\quad {{C(h)} = {\frac{1}{2}\quad \left( {{h = 1},2,\ldots \quad,7} \right)}}}{{{C(v)} = {\frac{1}{2\sqrt{2}}\quad \left( {v = 0} \right)}},\quad {{C(v)} = {\frac{1}{2}\quad \left( {{h = 1},2,\ldots \quad,7} \right)}}}{{\alpha \equiv \frac{\pi \quad {v\left( {{2y} + 1} \right)}}{16}},\quad {\beta \equiv {\frac{\pi \quad {h\left( {{2x} + 1} \right)}}{16}.}}}}} & (18)\end{matrix}$

An example of an 8-8 DCT device (called a “first technology” in thisapplication) is disclosed in the Japanese Patent Application Laid-openNo. Hei5-181896, in which the 8-8 DCT is performed on every blockcomposed of “8×8” picture element data constituting image data, which isconstructed of a product obtained by multiplying eight pieces of pictureelement data arranged in a transverse direction by eight pieces ofpicture element data arranged in a longitudinal direction, in accordancewith following equation (19) and equation (20). $\begin{matrix}\left. \begin{matrix}{\begin{bmatrix}F_{0} \\F_{4} \\F_{2} \\F_{6}\end{bmatrix} = {\begin{bmatrix}{a_{0} + a_{1} + a_{3} + a_{2}} & 0 & 0 \\{a_{0} - a_{1} + a_{3} - a_{2}} & 0 & 0 \\0 & {a_{0} - a_{3}} & {a_{1} - a_{2}} \\0 & {{- a_{1}} - a_{2}} & {a_{0} - a_{3}}\end{bmatrix}\begin{bmatrix}P_{3} \\P_{5} \\P_{1}\end{bmatrix}}} \\{\begin{bmatrix}F_{1} \\F_{3} \\F_{5} \\F_{7}\end{bmatrix} = {\begin{bmatrix}a_{4} & a_{5} & a_{6} & a_{7} \\{- a_{6}} & a_{4} & {- a_{7}} & {- a_{5}} \\{- a_{5}} & a_{7} & a_{4} & a_{6} \\a_{7} & a_{6} & {- a_{5}} & a_{4}\end{bmatrix}\begin{bmatrix}P_{6} \\P_{4} \\P_{2} \\P_{0}\end{bmatrix}}}\end{matrix} \right\} & (19) \\\left. \begin{matrix}{{\frac{1}{2}\begin{bmatrix}{f_{0} + f_{4}} \\{f_{1} + f_{5}} \\{f_{2} + f_{6}} \\{f_{3} + f_{7}}\end{bmatrix}} = {\begin{bmatrix}{a_{0} + a_{3}} & a_{2} & a_{1} \\{a_{0} - a_{3}} & {- a_{1}} & a_{2} \\{a_{0} - a_{3}} & a_{1} & {- a_{2}} \\{a_{0} + a_{3}} & {- a_{2}} & {- a_{1}}\end{bmatrix}\begin{bmatrix}P_{3} \\P_{5} \\P_{1}\end{bmatrix}}} \\{{\frac{1}{2}\begin{bmatrix}{f_{0} - f_{4}} \\{f_{1} - f_{5}} \\{f_{2} - f_{6}} \\{f_{3} - f_{7}}\end{bmatrix}} = {\begin{bmatrix}a_{5} & a_{7} & {- a_{6}} & {- a_{4}} \\a_{6} & a_{5} & a_{4} & {- a_{7}} \\{- a_{7}} & {- a_{4}} & a_{5} & {- a_{6}} \\a_{4} & {- a_{6}} & {- a_{7}} & a_{5}\end{bmatrix}\begin{bmatrix}P_{6} \\P_{4} \\P_{2} \\P_{0}\end{bmatrix}}}\end{matrix} \right\} & (20)\end{matrix}$

In the 8-8 DCT devices, the 8-8 DCT and 8-8 IDCT are performed byarithmetic operations according to a determinant equation (19) anddeterminant equation (20) derived from the equation (17) and theequation (18).

The first technology disclosed in the above Japanese Patent ApplicationLaid-open No. Hei5-181896 includes two 8-8 DCT devices. One of the two8-8 DCT, which performs the 8-8 DCT by arithmetic operations accordingto the determinant equation (19), is composed of eight selectingcircuits adapted to select one piece of input data out of 8 pieces ofinput data (a0 to a7), seven fixed coefficient multipliers connected tothe selecting circuits and adapted to multiply each of selected signalsoutput from the selecting circuits by a different coefficient and 5types of adding/subtracting units connected to outputs of the fixedcoefficient multipliers and adapted to perform adding and subtractingoperations to each of output signals from the fixed coefficientmultipliers in a variety of differently combined ways and is soconfigured that three types of the adding/subtracting units out of thefive types of the adding/subtracting units are used for the cosinetransformation and the remaining two types of the adding/subtractingunits for the inverse cosine transformation and that eight cosinetransformation coefficients are obtained by switching, four times, theway of selecting data in the selecting circuits and by switching, fourtimes, the calculating way from the addition to subtraction or viceversa in the adding and subtracting units. However, input data (a0 toa7), when the cosine transformation is performed, include a0=x0+x7,a1=x1+x6, a2=x2+x5, a3=x3+x4, a4=x0−x7, a5=x1−x6, a6=x2−x5 and a7=x3−x4,which can be obtained from 8 input image data (x0 to x7). Input data (a0to a7), when the inverse cosine transformation is performed, includesa0=x0, a1=x6, a2=x2, a3=x4, a4=−x7, a5=x1, a6=−x5 and a7=x3, which canbe obtained from eight input image data (x0 to x7).

The other out of the two 8-8 DCT devices is composed of four selectingcircuits adapted to select one piece of input data out of eight piecesof input data (a0 to a7), four fixed coefficient multipliers connectedto the selecting circuits and adapted to multiply each of selectedsignals output from the selecting circuits by a different coefficientand five types of adding/subtracting units connected to outputs of thefixed coefficient multipliers and adapted to perform adding orsubtracting operations to each of output signals from the fixedcoefficient multipliers in a variety of differently combined ways and isso configured that two types of the adding/subtracting units out of thefour types of the adding/subtracting units are used for the cosinetransformation and the remaining two types of the adding/subtractingunits for the inverse cosine transformation and that eight cosinetransformation coefficients are obtained by switching, eight times, theway of selecting data in the selecting circuits, and by switching, eighttimes, the calculating way from the addition to subtraction or viceversa in the adding and subtracting units and by switching, eight times,the selection of two types of coefficients in the fixed coefficientmultipliers. Eight pieces of input data (a0 to a7) for this DCT deviceare the same as those for the above one out of the two DCT devices.

In both these two DCT devices, DCT coefficients can be calculated byperforming the DCT on input data obtained from each line composed ofeight pieces of picture element data, which constitutes the blockcomposed of 8×8 picture element data, arranged either in the transversedirection or in the longitudinal direction, that is, 64 DCT coefficientscan be obtained by performing the DCT first on input data obtained froma first line composed of the eight picture element data arranged, forexample, in the traverse direction and then sequentially on input dataobtained from a second line, third line, . . . , eighth line, each beingcomposed of the eight picture element data also arranged in the traversedirection. The DCT is used to transform data signals on a time-axis tosignal components in the frequency region.

Therefore, the 64 DCT coefficients obtained by the DCT device representfrequency components in the frequency region. The 64 DCT coefficientsare used for coding only low frequency components being centralized onthe upper left of the block composed of 8×8 picture element data, whichcan provide image data in which information contained in the 8×8 pictureelement block is compressed. Then, by performing the DCT applied singlyto the 8×8 picture element block also on all the 8×8 picture elementblocks contained in the image, an image data having informationcompressed for every 8×8 picture element block can be obtained fortransmission.

Moreover, an example of another DCT device (called a “second technology”in this application) which can use both the 8-8 DCT function and 2-4-8DCT (described later in detail) function is disclosed in the JapanesePatent Application Laid-open No. Hei6-243160. The second technologydevice is composed of a factor switching controller, a first sortingcircuit to sort data in accordance with control signals fed from thefactor switching controller, a first fourth-degree inner productcalculating circuit, a second sorting circuit to sort data in accordancewith control signals fed from the factor switching controller, an innerproduct calculating circuit for the 2-4-8 DCT to perform the 2-4-8 DCTin accordance with control signals fed from the factor switchingcontroller, an eighth-degree/fourth-degree inner product circuit toselect an inner product calculating circuit for the 8-8 DCT, afourth-degree inner product circuit to select either of functions of theinner product calculating circuit for 2-4-8 DCT or functions of theinner product calculating circuit for 8-8 DCT in accordance with controlsignals fed from the factor switching circuit and a third sortingcircuit to sort data in accordance with control signals fed from thefactor switching circuit.

However, in the one 8-8 DCT device out of the first technology, aninconvenience occurs in that the 2-4-8 DCT required in operations of adigital video cannot be easily performed. This is due to the followingreason. That is, the 2-4-8 DCT is performed in accordance with thefollowing equation (21) and the 2-4-8 IDCT in accordance with thefollowing equation (22). $\begin{matrix}\left. \begin{matrix}{{F\left( {h,v} \right)} = {{C(v)}{C(h)}{\sum\limits_{z = 0}^{3}{\sum\limits_{x = 0}^{7}\quad {\left\{ {{f\left( {x,{2z}} \right)} + {f\left( {x,{{2z} + 1}} \right)}} \right\} \cos \quad {\gamma \cdot \cos}\quad \beta}}}}} \\{{F\left( {h,{v + 4}} \right)} = {{C(v)}{C(h)}{\sum\limits_{z = 0}^{3}{\sum\limits_{x = 0}^{7}\quad {\left\{ {{f\left( {x,{2z}} \right)} + {f\left( {x,{{2z} + 1}} \right)}} \right\} \cos \quad {\gamma \cdot \cos}\quad \beta}}}}}\end{matrix} \right\} & (21)\end{matrix}$

where

v=0,1, . . . , 7

z=integer of y/2${{{C(h)} = {\frac{1}{2\sqrt{2}}\quad \left( {h = 0} \right)}},\quad {{C(h)} = {\frac{1}{2}\quad \left( {{h = 1},2,\ldots \quad,7} \right)}}}{{{C(v)} = {\frac{1}{2\sqrt{2}}\quad \left( {v = 0} \right)}},\quad {{C(v)} = {\frac{1}{2}\quad \left( {{v = 1},2,\ldots \quad,7} \right)}}}$${\gamma \equiv \frac{\pi \quad {v\left( {{2z} + 1} \right)}}{8}},\quad {\beta \equiv \frac{\pi \quad {h\left( {{2x} + 1} \right)}}{16}}$

$\begin{matrix}\left. \begin{matrix}{{f\left( {x,{2z}} \right)} = {\sum\limits_{v = 0}^{3}{\sum\limits_{h = 0}^{7}\quad {\left\{ {{C(v)}{C(h)}\left( {{F\left( {h,v} \right)} + {F\left( {h,{v + 4}} \right)}} \right)} \right\} \cos \quad {\gamma \cdot \cos}\quad \beta}}}} \\{{f\left( {x,{{2z} + 1}} \right)} = {\sum\limits_{v = 0}^{3}{\sum\limits_{h = 0}^{7}\quad {\left\{ {{C(v)}{C(h)}\left( {{F\left( {h,v} \right)} - {F\left( {h,{v + 4}} \right)}} \right)} \right\} \cos \quad {\gamma \cdot \cos}\quad \beta}}}}\end{matrix} \right\} & (22)\end{matrix}$

where

v=0,1, . . . , 7

z=integer of y/2${{{C(h)} = {\frac{1}{2\sqrt{2}}\quad \left( {h = 0} \right)}},\quad {{C(h)} = {\frac{1}{2}\quad \left( {{h = 1},2,\ldots \quad,7} \right)}}}{{{C(v)} = {\frac{1}{2\sqrt{2}}\quad \left( {v = 0} \right)}},\quad {{C(v)} = {\frac{1}{2}\quad \left( {{v = 1},2,\ldots \quad,7} \right)}}}$${\gamma \equiv \frac{\pi \quad {v\left( {{2z} + 1} \right)}}{8}},\quad {\beta \equiv \frac{\pi \quad {h\left( {{2x} + 1} \right)}}{16}}$

As is apparent from comparison between the equation (17) and equation(18) being used for the 8-8 DCT and 8-8 IDCT respectively and theequation (21) and equation (22) being used for the 2-4-8 DCT and 2-4-8IDCT respectively, fixed coefficients {values expressed as cosine valuesin the equation (17) and equation (18)} of the fixed coefficientmultipliers used in the 8-8 DCT device are different from those {valuesexpressed as cosine values in the equation (21) and equation (22)} ofthe fixed coefficient multiplier used in the 2-4-8 DCT device and,moreover, data to be multiplied by the above fixed coefficients are alsodifferent. Therefore, when the 2-4-8 DCT is to be performed on imagedata, the 2-4-8 DCT device has to be separately fabricated in a mannerbeing similar to the 8-8 DCT device disclosed in the above JapanesePatent Application Laid-open No. Hei6-243160.

Furthermore, in the DCT device disclosed as the second technology, boththe 8-8 DCT and the 2-4-8 DCT can be used. However, the DCT device,while it is operated in a mode to operate as a two-dimensional 4×8 DCTdevice, is so configured that control signals, for example, signals withlogic “1” are fed from the coefficient switching controller to the firstsorting circuit, second sorting circuit, eighth-degree/fourth-degreeinner product circuit, fourth-degree inner product circuit and thirdsorting circuit to implement the two-dimensional 4×8 DCT function and,when it is operated in a mode to operate as a two-dimensional 8×8 DCTdevice, is so configured that control signals, for example, signals withlogic “0” are fed from the coefficient switching controller to the firstsorting circuit, second sorting circuit, eighth-degree/fourth-degreeinner product circuit, fourth-degree inner product circuit and thirdsorting circuit to implement the two-dimensional 4×8 DCT function. Thatis, the device is so constructed that, every time input data is sortedin a sorting order determined by the control signals fed from thecoefficient switching controller, a predetermined inner productarithmetic operation is performed on the sorted data to obtain DCTcoefficients corresponding to control signals output from thecoefficient switching controller. As a result, the processing of datasorting is always required not only for the two-dimensional 4×8 DCT butalso for the two-dimensional 8×8 DCT. The data sorting and the selectionof circuits by control signals fed from the coefficient switchingcontroller to implement functions of the two-dimensional 4×8 DCT ortwo-dimensional 8×8 DCT, are inseparable from each other. That is, theconventional DCT device is so configured that the selection of circuitsadapted to implement the two-dimensional 4×8 DCT or two-dimensional 8×8DCT is made in a state in which the processing of sorting data isrequired in an inseparable manner. Therefore, if the data sorting iscarried out via a RAM (Random-Access Memory), repeated processing ofsorting data is necessary, thus causing much time to be taken sortingthe data and a delay in obtaining DCT coefficients and, if the datasorting is carried out via hardware, it causes an increased scale ofcircuits and a delay in the propagation of signals.

SUMMARY OF THE INVENTION

In view of the above, it is an object of the present invention toprovide a method for compressing image signals, a method fordecompressing compressed image signals, a compression processingapparatus and decompression processing apparatus which are capable ofachieving high-speed transformation by using fixed coefficients inodd-numbered positions as the fixed coefficients used in both2−2^(N−1)−2^(N) DCT and 2−2^(N−1)−2^(N) IDCT and which are capable ofreducing a circuit scale and of performing high speed transformation byincorporating 2−2^(N−1)−2^(N) DCT and 2−1^(N−1)−2^(N) IDCT functionsinto basic 2^(N)-2^(N) DCT and 2^(N)-2^(N) IDCT devices.

According to a first aspect of the present invention, there is provideda method for compressing image signals including:

a selection process of selecting 2^(N) pieces of picture element data fj(0≦j≦2^(N)−1) contained in one line or one string constituting a blockof 2^(N)×2^(N) (N being a natural number) pieces of picture element dataforming image data, for each of fixed coefficients Pk given in equation(1) and equation (2) shown below and determined in accordance with adiscrete cosine transformation rule;

a multiplication process of multiplying each piece of the selectedpicture element data by each of corresponding fixed coefficients Pk toobtain products;

an addition/subtraction process of performing adding operations and/orsubtracting operations between products obtained by the multiplicationprocess and determined in accordance with the discrete cosinetransformation rule; and

an output process of outputting a value obtained by theaddition/subtraction process as transformation coefficient data Fj foreach line or each string constituting the block of 2^(N)×2^(N) pictureelement data;

wherein, in the selection process, first set and second set of pictureelement data composed of 2^(N) pieces of picture element data containedin one line or one string constituting the block of 2^(N)×2^(N) piecesof picture element data are selected for each of fixed coefficients, outof the fixed coefficients Pk, with k in odd-numbered positions inequation (1) and equation (2) shown below, in a predetermined order, andwherein, in the multiplication process, the first set and second set ofpicture element data selected for each of the fixed coefficients with kin odd-numbered positions in the equation (1) and equation (2) aremultiplied by each of the fixed coefficients with k in odd-numberedpositions in the equation (1) and equation (2) to obtain the product;$\begin{matrix}{P_{k} = {\cos \left( \frac{\left( {N - 1 - k} \right)\pi}{2^{N + 1}} \right)}} & (23)\end{matrix}$

where

0≦k≦2^(N−1)−2

however, k=2^(N−1)−1 is excluded; $\begin{matrix}{P_{k} = \frac{1}{\sqrt{2}}} & (24)\end{matrix}$

where (k=2^(N−1)−1).

In the foregoing, a preferable mode is one wherein a sum of 2^(N) piecesof picture element data having “j” data contained in the picture elementdata fj, one being lower-numbered data and the other being the nextlower-numbered data and thereafter in the same manner, is selected asthe first set of picture element data to be selected in the selectionprocess and wherein a difference between 2^(N) pieces of picture elementdata having “j” data contained in the picture element data fj, one beinglower-numbered data and the other being the next lower-numbered data andthereafter in the same manner, is selected as the second set of pictureelement data to be selected in the selection process.

According to a second aspect of the present invention, there is provideda method for decompressing image signals including:

a selection process of selecting 2^(N) pieces of transformationcoefficient data Fj (0≦j≦2^(N)−1) contained in one line or one stringconstituting a block of 2^(N)×2^(N) (N being a natural number) pieces oftransformation coefficient data block forming transformation coefficientdata transmitted after being transformed by a discrete cosinetransformation rule, for each of fixed coefficients Pk given in equation(3) and equation (4) shown below and determined in accordance with thediscrete cosine transformation rule;

a multiplication process of multiplying each of the selectedtransformation coefficient data by each of the corresponding fixedcoefficients Pk to obtain products;

an addition/subtraction process of performing adding operation and/orsubtracting operation between products obtained by the multiplicationprocess which is determined in accordance with the discrete cosinetransformation rule;

an output process of outputting a value obtained by theaddition/subtraction process as picture element data fj for each line oreach string constituting the block of 2^(N)×2^(N) picture element data;

wherein, in the selection process, first set and second set oftransformation coefficient data composed of 2^(N) pieces oftransformation coefficient data contained in one line or one stringconstituting the block of 2^(N)×2^(N) pieces of transformationcoefficient data are selected for each of fixed coefficients, out of thefixed coefficients Pk, with k in odd-numbered positions

in the equation (3) and equation (4), in a predetermined order, andwherein, in the multiplication process, each of the first set and secondset of transformation coefficient data selected for each of the fixedcoefficients with k in odd-numbered position in the equation (3) andequation (4) is multiplied by each of the fixed coefficients with k inodd-numbered positions in said equation (3) and equation (4) to obtainthe product; $\begin{matrix}{P_{k} = {\cos \left( \frac{\left( {N - 1 - k} \right)\pi}{2^{N + 1}} \right)}} & (25)\end{matrix}$

 0≦k≦2^(N−1)−2

where k=2^(N−1)−1 is excluded; $\begin{matrix}{P_{k} = \frac{1}{\sqrt{2}}} & (26)\end{matrix}$

(k=2^(N−1)−1).

In the foregoing, it is preferable that the first set of transformationcoefficient data is a sum of transformation coefficient data composed ofone data selected from a first transformation data set containing “j”data constituting first half of the 2^(N) pieces of transformationcoefficient data Fj and containing 2^(N−1) pieces of transformationcoefficient data and transformation coefficient data composed of onedata selected from a second transformation data set containing “j” dataconstituting second half of the 2^(N) pieces of transformationcoefficient data Fj and containing 2^(N−1) pieces of transformationcoefficient data and wherein the second set of transformation data is adifference between transformation coefficient data composed of one dataselected from the first set of transformation data and transformationcoefficient data composed of one data selected from the second set oftransformation data.

According to a third aspect of the present invention, there is provideda method for compressing image signals including:

a selection process of selecting 2^(N) pieces of picture element data fj(0≦j≦2^(N−1)) contained in one line or one string constituting a blockof 2^(N)×2^(N) (N being a natural number) pieces of picture element datablock forming image data, for each of fixed coefficients Pk given inequation (5) and equation (6) shown below and determined in accordancewith the discrete cosine transformation rule;

a multiplication process of multiplying each of the selected pictureelement data by each of the corresponding fixed coefficients Pk toobtain products;

an addition/subtraction process of performing adding operation and/orsubtracting operation between products obtained by the multiplicationprocess and determined in accordance with the discrete cosinetransformation rule; and

an output process of outputting a value obtained by theaddition/subtraction process as transformation coefficient data Fj foreach line or each string constituting the block of 2^(N)×2^(N) pictureelement data;

wherein, in the selection process, in the case of 2^(N)-2^(N) discretecosine transformation, 2^(N) pieces of picture element data are selectedfrom 2^(N) pieces of picture element data contained in one line or onestring constituting the block of 2^(N)×2^(N) picture element data foreach of the fixed coefficients Pk determined by the 2^(N)-2^(N) discretecosine transformation in a predetermined order and wherein, in theselection process, in the case of 2−2^(N−1)−2^(N) discrete cosinetransformation, each of first set and second set of picture element dataeach being composed of 2^(N) pieces of picture element data to bemultiplied by each of fixed coefficients, out of the fixed coefficientsPk, with k in odd-numbered positions in the equation (5) and equation(6), is selected from 2^(N) pieces of picture element data contained inone line or one string constituting the block of 2^(N)×2^(N) pieces ofpicture element data in a predetermined order,

wherein, in the multiplication process, in the case of the 2^(N)-2^(N)discrete cosine transformation, each of the 2^(N) pieces of pictureelement data selected in the selection process is multiplied by each ofthe corresponding fixed coefficients out of the fixed coefficients Pk toobtain products and wherein, in the case of the 2−2^(N−1)−2^(N) discretecosine transformation, each of the first set and second set of pictureelement data selected based on corresponding fixed coefficient, out ofthe fixed coefficients Pk, with k in odd-numbered positions in theequation (5) and equation (6) is multiplied by the fixed coefficients,out of the fixed coefficients Pk, with k in odd-numbered positions inthe equation (5) and equation (6), and

wherein, in the addition/subtraction process, in the case of the2^(N)-2^(N) discrete cosine transformation, the adding operations and/orsubtracting operations are performed between products obtained by themultiplication process and determined in accordance with the 2^(N)-2^(N)discrete cosine transformation and wherein, in the case of the2−2^(N−1)−2^(N) discrete cosine transformation, the adding operationsand/or subtracting operations are performed between products obtained bythe multiplication process and determined in accordance with the2−2^(N−1)−2^(N) discrete cosine transformation rule; $\begin{matrix}{P_{k} = {\cos \quad \left( \frac{\left( {N - 1 - k} \right)\pi}{2^{N + 1}} \right)}} & (27)\end{matrix}$

 0≦k≦2^(N−1)−2

where k=2^(N−1)−1 is excluded; $\begin{matrix}{P_{k} = \frac{1}{\sqrt{2}}} & (28)\end{matrix}$

(k=2^(N−1)−1).

Also, it is preferable that the picture element data to be selected inthe block of 2^(N)-2^(N) discrete cosine transformation includes thefirst set of picture element data composed of the 2^(N) pieces ofpicture element data contained in one line or one string constitutingthe block of 2^(N)×2^(N) pieces of picture element data to be multipliedby each of the fixed coefficients, out of the fixed coefficients Pk,with k in odd-numbered positions in the equation (5) and equation (6)and the second set of picture element data composed of the 2^(N) piecesof picture element data to be multiplied by each of fixed coefficients,out of the fixed coefficients Pk, with k in odd-numbered positions inthe equation (5) and equation (6).

Also, it is preferable that the picture element data selected in theselection process is a sum and difference between picture element dataconstituting a predetermined pair of picture element data.

Also, it is preferable that the picture element data constituting thepredetermined pair of picture element data, in the case of the2−2^(N−1)−2^(N) discrete cosine transformation, are 2^(N) pieces ofpicture element data having “j” data contained in the picture elementdata fj, one being lower-numbered data and the other being the nextlower-numbered data.

Furthermore, it is preferable that the picture element data constitutingthe predetermined pair of picture element data, in the case of the2^(N)-2^(N) discrete cosine transformation, are picture element datacomposed of one data selected from the first transformation data setcontaining “j” data which constitutes first half of the 2^(N) pieces ofpicture element data Fj and containing 2^(N−1) pieces of picture elementdata and picture element data composed of one data selected from thesecond picture element data set containing “j” data which constitutessecond half of the 2^(N) pieces of picture element data fj andcontaining 2^(N−1) pieces of picture element data.

According to a fourth aspect of the present invention, there is provideda method for decompressing image signals including:

a selection process of selecting 2^(N) pieces of transformationcoefficient data Fj (0≦j≦2^(N)−1) contained in one line or one stringconstituting a block of 2^(N)×2^(N) (N being a natural number) pieces oftransformation coefficient data block forming transformation coefficientdata transmitted after being transformed by a discrete cosinetransformation rule, for each of fixed coefficients Pk given in equation(7) and equation (8) shown below and determined in accordance with thediscrete cosine transformation rule;

a multiplication process of multiplying each of the selectedtransformation coefficient data by each of the corresponding fixedcoefficients Pk to obtain products;

an addition/subtraction process of performing adding operations and/orsubtracting operations between products obtained by the multiplicationprocess and determined in accordance with the discrete cosinetransformation rule; and

an output process of outputting a value obtained by theaddition/subtraction process as picture element data fj for each line oreach string constituting the block of 2^(N)×2^(N) transformationcoefficient data;

wherein, in the selection process, in the case of 2^(N)-2^(N) inversediscrete cosine transformation, each of the 2^(N) pieces oftransformation coefficient data is selected from 2^(N) m pieces oftransformation coefficient data contained in one line or one stringconstituting the block of 2^(N)×2^(N) transformation coefficient datafor each of the fixed coefficients Pk determined by the 2^(N)-2^(N)inverse discrete cosine transformation method in a predetermined order,and wherein, in the selection process, in the case of 2−2^(N−1)−2^(N)inverse discrete cosine transformation, first set and second set oftransformation coefficient data each being composed of 2^(N) pieces oftransformation coefficient data contained in one line or one stringconstituting the block of 2^(N)×2^(N) pieces of transformationcoefficient data are selected for each of fixed coefficients, out of thefixed coefficients Pk, with k in odd-numbered positions in the equation(7) and equation (8) in a predetermined order,

wherein, in the multiplication process, in the case of the 2^(N)-2^(N)inverse discrete cosine transformation, each of the 2^(N) pieces ofpicture element data selected in the selection process is multiplied byeach of corresponding fixed coefficients out of the fixed coefficientsPk to obtain products and wherein, in the case of the 2−2^(N−1)−2^(N)inverse discrete cosine transformation, each of the first set and secondset of transformation coefficient data selected based on each ofcorresponding fixed coefficients, out of the fixed coefficients Pk, withk in odd-numbered positions in said equation (7) and equation (8) ismultiplied by each of the fixed coefficients, out of the fixedcoefficients Pk, with k in odd-numbered positions in the equation (7)and equation (8) to obtain products,

wherein, in the addition/subtraction process, in the case of the2^(N)-2^(N) inverse discrete cosine transformation, the addingoperations and/or subtracting operations are performed between productsobtained by the multiplication process and determined in accordance withthe 2^(N)-2^(N) discrete cosine transformation rule and wherein, in thecase of the 2−2^(N−1)−2^(N) inverse discrete cosine transformation, theadding operations and/or subtracting operations are performed betweenproducts obtained by the multiplication process and determined inaccordance with the 2−2^(N−1)−2^(N) discrete cosine transformation rule;$\begin{matrix}{P_{k} = {\cos \quad \left( \frac{\left( {N - 1 - k} \right)\pi}{2^{N + 1}} \right)}} & (29)\end{matrix}$

 0≦k≦2^(N−1)−2

where k=2^(N−1) is excluded; $\begin{matrix}{P_{k} = \frac{1}{\sqrt{2}}} & (30)\end{matrix}$

(k=2^(N−1)).

In the foregoing, a preferable mode is one wherein the transformationcoefficient data to be selected in the 2^(N)-2^(N) inverse discretecosine transformation includes the first set of transformationcoefficient data composed of the 2^(N) pieces of transformationcoefficient data contained in one line or one string constituting theblock of 2^(N)×2^(N) pieces of transformation coefficient data to bemultiplied by each of the fixed coefficients, out of the fixedcoefficients Pk, with k in odd-numbered positions in the equation (7)and equation (8) and the second set of transformation coefficient datacomposed of the 2^(N) pieces of transformation coefficient data to bemultiplied by each of fixed coefficients, out of the fixed coefficientsPk, with k in even-numbered positions in the equation (7) and equation(8).

According to a fifth aspect of the present invention, there is provideda device for compressing image signals comprising:

a selection circuit for selecting 2^(N) pieces of picture element datafj (0≦j≦2^(N)−1) contained in one line or one string constituting ablock of 2^(N)×2^(N) (N being a natural number) pieces of pictureelement data block forming image data, for each of fixed coefficients Pkgiven in equation (9) and equation (10) shown below and determined inaccordance with a discrete cosine transformation rule;

a multiplication circuit for multiplying each of the selected pictureelement data by each of the corresponding fixed coefficients Pk toobtain products;

an addition/subtraction circuit for performing adding operations and/orsubtracting operations between products obtained by the multiplicationprocess and determined in accordance with the discrete cosinetransformation rule; and

an output circuit for outputting a value obtained by the addingoperations and/or subtracting operations as trans-formation coefficientdata Fj for each line or each string constituting the block of2^(N)×2^(N) picture element data;

wherein the selection circuit is that each of the first set and secondset of picture element data composed of 2^(N) pieces of picture elementdata contained in one line or one string constituting the block of2^(N)×2^(N) pieces of picture element data is selected for each of fixedcoefficients, out of the fixed coefficients Pk, with k in odd-numberedpositions in equation (9) and equation (10) shown below, in apredetermined order, and wherein, in the multiplication process, each ofthe first set and second set of picture element data selected for eachof the fixed coefficients with kin odd-numbered positions in theequation (9) and equation (10) is multiplied by the fixed coefficientwith k in odd-numbered positions in the equation (9) and equation (10)to obtain the product; $\begin{matrix}{P_{k} = {\cos \quad \left( \frac{\left( {N - 1 - k} \right)\pi}{2^{N + 1}} \right)}} & (31)\end{matrix}$

 0≦k≦2^(N−1)−2

where k=2^(N−1)−1 is excluded; $\begin{matrix}{P_{k} = \frac{1}{\sqrt{2}}} & (32)\end{matrix}$

(k=2^(N−1)−1).

In the foregoing, a preferable mode is one wherein a sum of 2^(N) piecesof picture element data having “j” data contained in the picture elementdata fj, one being lower-numbered data and the other being the nextlower-numbered data and thereafter in the same manner, is selected bythe selection circuit as the first set of picture element data andwherein a difference between 2^(N) pieces of picture element data having“j” data contained in the picture element data fj, one beinglower-numbered data and the other being the next lower-numbered data,and thereafter in the same manner, is selected by the selection circuitas the second set of picture element.

According to a sixth aspect of the present invention, there is provideda device for decompressing image signals including:

a selection circuit for selecting 2^(N) pieces of transformationcoefficient data Fj (0≦j≦2^(N)−1) contained in one line or one stringconstituting a block of 2^(N)×2^(N) (N being a natural number) pieces oftransformation coefficient data block forming transformation coefficientdata transmitted after being transformed by a discrete cosinetransformation method, for each of fixed coefficients Pk given inequation (11) and equation (12) shown below and determined in accordancewith a discrete cosine transformation rule;

a multiplication circuit for multiplying each of the selectedtransformation coefficient data by each of the corresponding fixedcoefficient Pk to obtain products;

an addition/subtraction circuit for performing adding operations and/orsubtracting operations between products obtained by the multiplicationprocess which is determined in accordance with the discrete cosinetransformation rule; and

an output circuit for outputting a value obtained by the addingoperations and/or subtracting operations as picture element data fj foreach line or each string constituting the block of 2^(N)×2^(N) pictureelement data;

wherein the selection circuit is that each of the first set and secondset of transformation coefficient data composed of 2^(N) pieces oftransformation coefficient data contained in one line or one stringconstituting the block of 2^(N)×2^(N) pieces of transformationcoefficient datablock is selected for each of fixed coefficients, out ofthe fixed coefficients Pk, with k in odd-numbered positions in theequation (11) and equation 12), in a predetermined order, and whereinthe multiplication circuit is that each of the first set and second setof transformation coefficient data selected for each of the fixedcoefficients with kin odd-numbered positions in the equation (11) andequation (12) is multiplied by each of the fixed coefficients with k inodd-numbered positions in the equation (11) and equation (12) to obtainthe product; $\begin{matrix}{P_{k} = {\cos \quad \left( \frac{\left( {N - 1 - k} \right)\pi}{2^{N + 1}} \right)}} & (33)\end{matrix}$

 0≦k≦2^(N−1)−2

where k=2^(N−1)−1 is excluded; $\begin{matrix}{P_{k} = \frac{1}{\sqrt{2}}} & (34)\end{matrix}$

(k=2^(N−1)−1).

In the foregoing, a preferable mode is one wherein the selectioncircuit, selects, as the first set of transformation coefficient data, asum of transformation coefficient data composed of one data selectedfrom a first transformation data set containing “j” data whichconstitutes first half of the 2^(N) pieces of transformation coefficientdata Fj and containing 2^(N−1) pieces of transformation coefficient dataand transformation coefficient data composed of one data selected from asecond transformation data set containing “j” data which constitutessecond half of the 2^(N) pieces of transformation coefficient data Fjand containing 2^(N−1) pieces of transformation coefficient data andwherein the selection circuit, selects, as the second set oftransformation data, a difference between transformation coefficientdata composed of one data selected from the first transformation dataset and transformation coefficient data composed of one data selectedfrom the second transformation data set.

According to a seventh aspect of the present invention, there isprovided a device for compressing image signals including:

a selection circuit for selecting 2^(N) pieces of picture element datafj (0≦j≦2^(N)−1) contained in one line or one string constituting ablock of 2^(N)×2^(N) (N being a natural number) pieces of pictureelement data block forming image data, for each of fixed coefficients Pkgiven in equation (13) and equation (14) shown below and determined inaccordance with a discrete cosine transformation rule;

a multiplication circuit for multiplying each of the selected pictureelement data by each of the corresponding fixed coefficients Pk toobtain products;

an addition/subtraction circuit for performing adding operations and/orsubtracting operations between products obtained by the multiplicationcircuit and determined in accordance with the discrete cosinetransformation rule; and

an output circuit for outputting a value obtained by the addingoperations and/or subtracting operations as trans-formation coefficientdata Fj for each line or each string constituting the block of2^(N)×2^(N) picture element data;

wherein the selection circuit, in the case of 2^(N)-2^(N) discretecosine transformation, selects 2^(N) pieces of picture element data from2 ^(N) pieces of picture element data contained in one line or onestring constituting the block of 2^(N)×2^(N) picture element data blockfor each of the fixed coefficients Pk determined by the 2^(N)-2^(N)discrete cosine transformation method in a predetermined order andwherein the selection circuit, in the case of 2−2^(N−1)−2^(N) discretecosine transformation, selects each of first set and second set ofpicture element data each being composed of 2^(N) pieces of pictureelement data to be multiplied by each of fixed coefficients, out of thefixed coefficients Pk, with k in odd-numbered positions in the equation(13) and equation (14), from 2^(N) pieces of picture element datacontained in one line or one string constituting the block of2^(N)×2^(N) pieces of picture element data block in a predeterminedorder,

wherein the multiplication circuit, in the case of the 2^(N)-2^(N)discrete cosine transformation, multiplies each of the 2^(N) pieces ofpicture element data selected by the selection circuit by each ofcorresponding fixed coefficients out of the fixed coefficients Pk toobtain products and wherein the multiplication circuit, in the case ofthe 2−2^(N−1)−2^(N) discrete cosine transformation, multiplies each ofthe first set and second set of picture element data selected based oneach of corresponding fixed coefficients, out of the fixed coefficientsPk, with k in odd-numbered positions in the equation (13) and equation(14) by each of the fixed coefficients, out of the fixed coefficientsPk, with k in odd-numbered positions the equation (13) and equation(14), and

wherein the addition/subtraction circuit, in the case of the 2^(N)-2^(N)discrete cosine transformation, performs the adding operations and/orsubtracting operations between products obtained by the multiplicationprocess and determined in accordance with the 2^(N)-2^(N) discretecosine transformation and wherein the addition/subtraction circuit, inthe case of the 2−2^(N−1)−2^(N) discrete cosine transformation, performsthe adding operations and/or subtracting operations between productsobtained by the multiplication process and determined in accordance withthe 2−2^(N−1)−2^(N) discrete cosine transformation rule; $\begin{matrix}{P_{k} = {\cos \quad \left( \frac{\left( {N - 1 - k} \right)\pi}{2^{N + 1}} \right)}} & (35)\end{matrix}$

 0≦k≦2^(N−1)−2

where k=2^(N−1)−1 is excluded; $\begin{matrix}{P_{k} = \frac{1}{\sqrt{2}}} & (36)\end{matrix}$

(k=2^(N−1)−1).

In the foregoing, a preferable mode is one wherein the picture elementdata to be selected in said 2^(N)-2^(N) discrete cosine transformationincludes the first set of picture element data composed of the 2^(N)pieces of picture element data contained in one line or one stringconstituting the block of 2^(N)×2^(N) pieces of picture element datablock to be multiplied by each of the fixed coefficients, out of thefixed coefficients Pk, with k in odd-numbered positions in the equation(13) and equation (14) and the second set of picture element datacomposed of the 2^(N) pieces of picture element data to be multiplied byeach of fixed coefficients, out of the fixed coefficients Pk, with k inodd-numbered positions in the equation (13) and equation (14).

Also, a preferable mode is one wherein the selection circuit, selects,as the picture element data, a sum and difference between pictureelement data constituting a predetermined pair of picture element.

Also, a preferable mode is one wherein the selection circuit selects, asthe picture element data constituting the predetermined pair of pictureelement data, in the case of the 2−2^(N−1)−2^(N) discrete cosinetransformation, 2^(N) pieces of picture element data having “j” datacontained in the picture element data fj, one being lower-numbered dataand the other being the next lower-numbered data.

Also, a preferable mode is one wherein the selection circuit selects, asthe picture element data constituting the predetermined pair of pictureelement data, in the case of the 2^(N)-2^(N) discrete cosinetransformation, picture element data composed of one data selected fromthe first transformation data set containing “j” data constituting firsthalf of the 2^(N) pieces of picture element data Fj and containing2^(N−1) pieces of picture element data and picture element data composedof one data selected from the second picture element data set containing“j” data constituting second half of the 2^(N) pieces of picture elementdata fj and containing 2^(N) pieces of picture element data.

According to an eighth aspect of the present invention, there isprovided a device for decompressing image signals including:

a selection circuit for selecting 2^(N) pieces of transformationcoefficient data Fj (0≦j≦2^(N)−1) contained in one line or one stringconstituting a block of 2^(N)×2^(N) (N being a natural number) pieces oftransformation coefficient data block forming transformation coefficientdata transmitted after being transformed by a discrete cosinetransformation method, for each of fixed coefficients Pk given inequation (15) and equation (16) shown below and determined in accordancewith a discrete cosine transformation rule;

a multiplication circuit for multiplying each of the selectedtransformation coefficient data by each of the corresponding fixedcoefficients Pk to obtain products;

an addition/subtraction circuit for performing adding operations and/orsubtracting operations between products obtained by the multiplicationcircuit and determined in accordance with the discrete cosinetransformation rule; and

an output circuit for outputting a value obtained by the addingoperations and/or subtracting operations as picture element data fj foreach line or each string constituting the block of 2^(N)×2^(N)transformation coefficient data;

wherein the selection circuit, in the case of 2^(N)-2^(N) inversediscrete cosine transformation, selects 2^(N) pieces of transformationcoefficient data from 2^(N) pieces of transformation coefficient datacontained in one line or one string constituting the block of2^(N)×2^(N) transformation coefficient data for each of the fixedcoefficients Pk determined by the 2^(N)-2^(N) inverse discrete cosinetransformation rule in a predetermined order, and wherein the selectioncircuit, in the case of 2−2^(N−1)−2^(N) inverse discrete cosinetransformation, selects first set and second set of transformationcoefficient data each being composed of 2^(N) pieces of transformationcoefficient data contained in one line or one string constituting theblock of 2^(N)×2^(N) pieces of transformation coefficient data for eachof fixed coefficients, out of the fixed coefficients Pk, with k inodd-numbered positions in the equation (15) and equation (16) in apredetermined order,

wherein, the multiplication circuit, in the case of the 2^(N)-2^(N)inverse discrete cosine transformation, multiplies each of 2^(N) piecesof picture element data selected in the selection process by each ofcorresponding fixed coefficients, out of the fixed coefficients Pk, toobtain products and wherein the multiplication circuit, in the case ofthe 2−2^(N−1)−2^(N) inverse discrete cosine transformation, multiplieseach of the first set and second set of transformation coefficient dataselected based on each of corresponding fixed coefficients, out of thefixed coefficients Pk, with k in odd-numbered positions in the equation(15) and equation (16) by each of the fixed coefficients, out of thefixed coefficients Pk, with k in odd-numbered positions in the equation(15) and equation (16) to obtain products,

wherein, the addition/subtraction circuit, in the case of the2^(N)-2^(N) inverse discrete cosine transformation, performs the addingoperations and/or subtracting operations between products obtained bythe multiplication circuit and determined in accordance with the2^(N)-2^(N) discrete cosine transformation and wherein, theaddition/subtraction circuit, in the case of the 2−2^(N−1)−2^(N) inversediscrete cosine transformation, performs the adding operations and/orsubtracting operations between products obtained by the multiplicationprocess and determined in accordance with the 2−2^(N−1)−2^(N) discretecosine transformation; $\begin{matrix}{P_{k} = {\cos \left( \frac{\left( {N - 1 - k} \right)\pi}{2^{N + 1}} \right)}} & (37)\end{matrix}$

 0≦k≦2^(N−1)−2

where k=2^(N−1)−1 is excluded; $\begin{matrix}{P_{k} = \frac{1}{\sqrt{2}}} & (38)\end{matrix}$

(k=2^(N−1)−1).

Furthermore, a preferable mode is one wherein the selection circuit, insaid 2^(N)-2^(N) inverse discrete cosine transformation, as thetransformation coefficient data, selects the first set of transformationcoefficient data composed of the 2^(N) pieces of transformationcoefficient data contained in one line or one string constituting theblock of 2^(N)×2^(N) pieces of transformation coefficient data to bemultiplied by each of the fixed coefficients, out of the fixedcoefficients Pk, with k in odd-numbered positions in said equation (15)and equation (16) and the second set of transformation coefficient datacomposed of the 2^(N) pieces of transformation coefficient data to bemultiplied by each of fixed coefficients, out of the fixed coefficientsPk, with k in even-numbered in said equation (15) and equation (16).

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages and features of the presentinvention will be more apparent from the following description taken inconjunction with the accompanying drawings in which:

FIG. 1 is a schematic block diagram showing electrical configurations ofan 8-8/2-4-8 DCT device according to a first embodiment of the presentinvention;

FIG. 2 is a schematic block diagram partially showing electricalconfigurations of the 8-8 /2-4-8 DCT device according to the firstembodiment of the present invention;

FIG. 3 shows apart of an operational timing chart explaining 8-8 DCT inthe 8-8/2-4-8 DCT device according to the first embodiment of thepresent invention;

FIG. 4 shows a residual part of the operational timing chart explainingthe 8-8 DCT in the 8-8/2-4-8 DCT device according to the firstembodiment of the present invention;

FIG. 5 shows apart of an operational timing chart explaining 2-4-8 DCTin the 8-8/2-4-8 DCT device according to the first embodiment of thepresent invention;

FIG. 6 shows a residual part of the operational timing chart explainingthe 2-4-8 DCT in the 8-8/2-4-8 DCT device according to the firstembodiment of the present invention;

FIG. 7 is a schematic block diagram partially showing configurations ofthe 8-8/2-4-8 IDCT device according to a second embodiment of thepresent invention;

FIG. 8 is also a schematic block diagram partially showingconfigurations of an 8-8/2-4-8 IDCT device according to the secondembodiment of the present invention;

FIG. 9 is a part of a timing chart explaining operations of an 8-8 IDCTconstituting the 8-8 /2-4-8 IDCT device according to the secondembodiment of the present invention;

FIG. 10 is a residual part of the timing chart explaining operations ofthe 8-8 IDCT constituting the 8-8/2-4-8 IDCT according to the secondembodiment of the present invention;

FIG. 11 is a part of a timing chart explaining operations of an 2-4-8IDCT constituting the 8-8/2-4-8 IDCT according to the second embodimentof the present invention;

FIG. 12 is a residual part of the timing chart explaining operations ofthe 2-4-8 IDCT constituting the 8-8/2-4-8 IDCT according to the secondembodiment of the present invention;

FIG. 13 is a schematic block diagram partially showing electricalconfigurations of a 16-16/2-8-16 DCT device according to a thirdembodiment of the present invention;

FIG. 14 is a schematic block diagram partially showing electricalconfigurations of the 16-16/2-8-16 DCT device according to the thirdembodiment of the present invention;

FIG. 15 is a schematic block diagram partially showing electricalconfigurations of a 16-16/2-8-16 IDCT device according to a fourthembodiment of the present invention; and

FIG. 16 is a schematic block diagram partially showing electricalconfigurations of the 16-16/2-8-16 IDCT device according to the fourthembodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Best modes of carrying out the present invention will be described infurther detail using various embodiments with reference to theaccompanying drawings.

First Embodiment

FIG. 1 is a schematic block diagram showing electrical configurations ofan 8-8 DCT/2-4-8 DCT device according to a first embodiment of thepresent invention. FIG. 2 is a schematic block diagram partially showingelectrical configurations of the 8-8 DCT/2-4-8 DCT device according tothe first embodiment. FIG. 3 shows a part of an operational timing chartexplaining the 8-8 DCT in the 8-8 DCT/2-4-8 DCT device according to thefirst embodiment. FIG. 4 shows the residual part of the operationaltiming chart explaining the 8-8 DCT in the 8-8 DCT/2-4-8 DCT deviceaccording to the first embodiment. FIG. 5 shows a part of an operationaltiming chart explaining the 2-4-8 DCT in the 8-8 DCT/2-4-8 DCT deviceaccording to the first embodiment. FIG. 6 shows the residual part of theoperational timing chart explaining the 2-4-8 DCT in the 8-8 DCT/2-4-8DCT device according to the first embodiment. By overlaying a line I—Iin FIG. 1 on a line I—I in FIG. 2, an overall configuration of the 8-8DCT/2-4-8 DCT device can be shown.

Thus, according to the first embodiment, since the 8-8 DCT/2-4-8 DCTdevice is so configured that a part of the 8-8 DCT circuit can be usedfor the 2-4-8 DCT, a high-speed calculating characteristic obtainedthrough a pipeline processing type arithmetic operation in the 8-8 DCTcan be maintained in the 2-4-8 DCT and the high-speed calculatingcharacteristics can be still maintained in even miniaturized 8-8 DCT and2-4-8 DCT devices.

Prior to description of configurations of the 8-8 DCT/2-4-8 DCT device,operational equations used to perform the 8-8 DCT on every one line orone string constituting 8×8 picture element data are first explainedbelow.

By expressing the two-dimensional equation (17) described in the above“Description of the Related Art” in the form of one dimensional equation(39) and by decompressing the equation (39) with respect to h and x, theequation (39) is expressed by an equation (40). Where, P₀ to P₆ are asfollows:

P₀=cos(7π/16)=−cos(9π/16)=0.195090322 . . .

P₁=cos(6π/16)=−cos(10π/16)=0.382683432 . . .

P₂=cos(5π/16)=−cos(11π/16)=0.55557023 . . .

P₃=cos(4π/16)=−cos(12π/16)=0.707106781 . . .

P₄=cos(3π/16)=−cos(13π/16)=0.831469612 . . .

P₅=cos(2π/16)=−cos(14π/16)=0.923879532 . . .

P₆=cos(π/16)=−cos(15π/16)=0.980785280 . . . $\begin{matrix}\begin{matrix}{{F(h)} = \quad {{C(h)}{\sum\limits_{x = 0}^{7}{{f\left( {x,y} \right)}{\cos \left( \frac{\pi \quad {h\left( {{2x} + 1} \right)}}{16} \right)}}}}} \\{= \quad {{C(h)}\left\{ {{{f\left( {0,y} \right)}{\cos \left( \frac{\pi \quad h}{16} \right)}} + {{f\left( {1,y} \right)}{\cos \left( \frac{3\quad \pi \quad h}{16} \right)}} + {{f\left( {2,y} \right)}{\cos \left( \frac{5\quad \pi \quad h}{16} \right)}} +} \right.}} \\{\quad {{{f\left( {3,y} \right)}{\cos \left( \frac{7\quad \pi \quad h}{16} \right)}} + {{f\left( {4,y} \right)}{\cos \left( \frac{9\quad \pi \quad h}{16} \right)}} + {{f\left( {5,y} \right)}{\cos \left( \frac{11\quad \pi \quad h}{16} \right)}} +}} \\{\quad \left. {{{f\left( {6,y} \right)}{\cos \left( \frac{13\quad \pi \quad h}{16} \right)}} + {{f\left( {7,y} \right)}{\cos \left( \frac{15\quad \pi \quad h}{16} \right)}}} \right\}}\end{matrix} & (39) \\{\left. \begin{matrix}\begin{matrix}{{(i)\quad {F(0)}} = \quad {\frac{1}{2\sqrt{2}}\left\{ {{{f\left( {0,y} \right)} \cdot 1} + {{f\left( {1,y} \right)} \cdot 1} + {{f\left( {2,y} \right)} \cdot 1} + {{f\left( {3,y} \right)} \cdot 1} +} \right.}} \\{\quad \left. {{{f\left( {4,y} \right)} \cdot 1} + {{f\left( {5,y} \right)} \cdot 1} + {{f\left( {6,y} \right)} \cdot 1} + {{f\left( {7,y} \right)} \cdot 1}} \right\}} \\{= \quad {\frac{1}{2}\left\{ {{{f\left( {0,y} \right)} \cdot \frac{1}{\sqrt{2}}} + {{f\left( {1,y} \right)} \cdot \frac{1}{\sqrt{2}}} + {{f\left( {2,y} \right)} \cdot \frac{1}{\sqrt{2}}} +} \right.}} \\{\quad {{{{f\left( {3,y} \right)} \cdot \frac{1}{\sqrt{2}}}{{f\left( {4,y} \right)} \cdot \frac{1}{\sqrt{2}}}} + {{f\left( {5,y} \right)} \cdot \frac{1}{\sqrt{2}}} +}} \\{\quad \left. {{{f\left( {6,y} \right)} \cdot \frac{1}{\sqrt{2}}} + {{f\left( {7,y} \right)} \cdot \frac{1}{\sqrt{2}}}} \right\}} \\{= \quad {\frac{1}{2}\left\{ {{{f\left( {0,y} \right)} \cdot P_{3}} + {{f\left( {1,y} \right)} \cdot P_{3}} + {{f\left( {2,y} \right)} \cdot P_{3}} +} \right.}} \\{\quad {{{f\left( {3,y} \right)} \cdot P_{3}} + {{f\left( {4,y} \right)} \cdot P_{3}} + {{f\left( {5,y} \right)} \cdot P_{3}} +}} \\{\quad \left. {{{f\left( {6,y} \right)} \cdot P_{3}} + {{f\left( {7,y} \right)} \cdot P_{3}}} \right\}}\end{matrix} \\\begin{matrix}{{({ii})\quad {F(1)}} = \quad {\frac{1}{2}\left\{ {{{f\left( {0,y} \right)} \cdot P_{6}} + {{f\left( {1,y} \right)} \cdot P_{4}} + {{f\left( {2,y} \right)} \cdot P_{2}} +} \right.}} \\{\quad {{{f\left( {3,y} \right)} \cdot P_{0}} + {{f\left( {4,y} \right)} \cdot \left( {- P_{0}} \right)} + {{f\left( {5,y} \right)} \cdot \left( {- P_{2}} \right)} +}} \\{\quad \left. {{{f\left( {6,y} \right)} \cdot \left( {- P_{4}} \right)} + {{f\left( {7,y} \right)} \cdot \left( {- P_{6}} \right)}} \right\}}\end{matrix} \\\begin{matrix}{{({iii})\quad {F(2)}} = \quad {\frac{1}{2}\left\{ {{{f\left( {0,y} \right)} \cdot P_{5}} + {{f\left( {1,y} \right)} \cdot P_{6}} + {{f\left( {2,y} \right)} \cdot \left( {- P_{1}} \right)} +} \right.}} \\{\quad {{{f\left( {3,y} \right)} \cdot \left( {- P_{5}} \right)} + {{f\left( {4,y} \right)} \cdot \left( {- P_{5}} \right)} + {{f\left( {5,y} \right)} \cdot \left( {- P_{1}} \right)} +}} \\{\quad \left. {{{f\left( {6,y} \right)} \cdot P_{1}} + {{f\left( {7,y} \right)} \cdot P_{5}}} \right\}}\end{matrix} \\\begin{matrix}{{({iv})\quad {F(3)}} = \quad {\frac{1}{2}\left\{ {{{f\left( {0,y} \right)} \cdot P_{4}} + {{f\left( {1,y} \right)} \cdot \left( {- P_{0}} \right)} + {{f\left( {2,y} \right)} \cdot \left( {- P_{6}} \right)} +} \right.}} \\{\quad {{{f\left( {3,y} \right)} \cdot P_{2}} + {{f\left( {4,y} \right)} \cdot \left( {- P_{2}} \right)} + {{f\left( {5,y} \right)} \cdot P_{6}} +}} \\{\quad \left. {{{f\left( {6,y} \right)} \cdot P_{0}} + {{f\left( {7,y} \right)} \cdot \left( {- P_{4}} \right)}} \right\}}\end{matrix} \\\begin{matrix}{{(v)\quad {F(4)}} = \quad {\frac{1}{2}\left\{ {{{f\left( {0,y} \right)} \cdot P_{3}} + {{f\left( {1,y} \right)} \cdot \left( {- P_{3}} \right)} + {{f\left( {2,y} \right)} \cdot \left( {- P_{3}} \right)} +} \right.}} \\{\quad {{{f\left( {3,y} \right)} \cdot P_{3}} + {{f\left( {4,y} \right)} \cdot P_{3}} + {{f\left( {5,y} \right)} \cdot \left( {- P_{3}} \right)} +}} \\{\quad \left. {{{f\left( {6,y} \right)} \cdot \left( {- P_{3}} \right)} + {{f\left( {7,y} \right)} \cdot P_{3}}} \right\}}\end{matrix} \\\begin{matrix}{{({vi})\quad {F(5)}} = \quad {\frac{1}{2}\left\{ {{{f\left( {0,y} \right)} \cdot P_{2}} + {{f\left( {1,y} \right)} \cdot \left( {- P_{6}} \right)} + {{f\left( {2,y} \right)} \cdot \left( {- P_{0}} \right)} +} \right.}} \\{\quad {{{f\left( {3,y} \right)} \cdot P_{4}} + {{f\left( {4,y} \right)} \cdot \left( {- P_{4}} \right)} + {{f\left( {5,y} \right)} \cdot P_{0}} +}} \\{\quad \left. {{{f\left( {6,y} \right)} \cdot P_{6}} + {{f\left( {7,y} \right)} \cdot \left( {- P_{2}} \right)}} \right\}}\end{matrix} \\\begin{matrix}{{({vii})\quad {F(6)}} = \quad {\frac{1}{2}\left\{ {{{f\left( {0,y} \right)} \cdot P_{1}} + {{f\left( {1,y} \right)} \cdot \left( {- P_{5}} \right)} + {{f\left( {2,y} \right)} \cdot \left( {- P_{5}} \right)} +} \right.}} \\{\quad {{{f\left( {3,y} \right)} \cdot \left( {- P_{4}} \right)} + {{f\left( {4,y} \right)} \cdot \left( {- P_{1}} \right)} + {{f\left( {5,y} \right)} \cdot P_{5}} +}} \\{\quad \left. {{{f\left( {6,y} \right)} \cdot \left( {- P_{5}} \right)} + {{f\left( {7,y} \right)} \cdot P_{1}}} \right\}}\end{matrix} \\\begin{matrix}{{({viii})\quad {F(7)}} = \quad {\frac{1}{2}\left\{ {{{f\left( {0,y} \right)} \cdot P_{0}} + {{f\left( {1,y} \right)} \cdot P_{2}} + {{f\left( {2,y} \right)} \cdot P_{4}} +} \right.}} \\{\quad {{{f\left( {3,y} \right)} \cdot P_{6}} + {{f\left( {4,y} \right)} \cdot \left( {- P_{6}} \right)} + {{f\left( {5,y} \right)} \cdot \left( {- P_{4}} \right)} +}} \\{\quad \left. {{{f\left( {6,y} \right)} \cdot \left( {- P_{2}} \right)} + {{f\left( {7,y} \right)} \cdot \left( {- P_{0}} \right)}} \right\}}\end{matrix}\end{matrix} \right\} {}} & (40)\end{matrix}$

Then, when the equation (40) is changed by setting so that F(0)=F₀,F(1)=F₁, F(2)=F₂, F(3)=F₃, F(4)=F₄, F(5)=F₅, F(6)=F₆ and F(7)=F₇ and sothat f(0, y)=f₀, f(1, y)=f₁, f(2, y)=f₂, f(3, y)=f₃, f(4, y)=f₄, f(5,y)=f₅, f(6, y)=f₆ and f(7, y)=f₇, the equation (40) is expressed by anequation (41). By changing the right side of the equation (41), anequation (42) can be obtained. $\begin{matrix}{\begin{bmatrix}F_{0} \\F_{1} \\F_{2} \\F_{3} \\F_{4} \\F_{5} \\F_{6} \\F_{7}\end{bmatrix} = {\begin{bmatrix}P_{3} & P_{3} & P_{3} & P_{3} & P_{3} & P_{3} & P_{3} & P_{3} \\P_{6} & P_{4} & P_{2} & P_{0} & {- P_{0}} & {- P_{2}} & {- P_{4}} & {- P_{6}} \\P_{5} & P_{1} & {- P_{1}} & {- P_{5}} & {- P_{5}} & {- P_{1}} & P_{1} & P_{5} \\P_{4} & {- P_{0}} & {- P_{6}} & P_{2} & {- P_{2}} & P_{6} & P_{0} & {- P_{4}} \\P_{3} & {- P_{3}} & {- P_{3}} & P_{3} & P_{3} & {- P_{3}} & {- P_{3}} & P_{3} \\P_{2} & {- P_{6}} & {- P_{0}} & P_{4} & {- P_{4}} & P_{0} & P_{6} & {- P_{2}} \\P_{1} & {- P_{5}} & P_{5} & {- P_{4}} & {- P_{1}} & P_{5} & {- P_{5}} & P_{1} \\P_{0} & P_{2} & P_{4} & P_{6} & {- P_{6}} & {- P_{4}} & {- P_{2}} & {- P_{0}}\end{bmatrix}\begin{bmatrix}f_{0} \\f_{1} \\f_{2} \\f_{3} \\f_{4} \\f_{5} \\f_{6} \\f_{7}\end{bmatrix}}} & (41) \\{\begin{bmatrix}F_{0} \\F_{1} \\F_{2} \\F_{3} \\F_{4} \\F_{5} \\F_{6} \\F_{7}\end{bmatrix} = {\begin{bmatrix}P_{3} & P_{3} & P_{3} & P_{3} & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & P_{6} & P_{4} & P_{2} & P_{0} \\P_{5} & {- P_{1}} & {- P_{1}} & {- P_{5}} & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & P_{4} & {- P_{0}} & {- P_{6}} & P_{2} \\P_{3} & {- P_{3}} & {- P_{3}} & P_{3} & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & P_{2} & {- P_{6}} & {- P_{0}} & {- P_{4}} \\P_{1} & {- P_{5}} & P_{5} & {- P_{1}} & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & P_{0} & P_{2} & P_{4} & P_{6}\end{bmatrix}\begin{bmatrix}{f_{0} + f_{7}} \\{f_{1} + f_{6}} \\{f_{2} + f_{5}} \\{f_{3} + f_{4}} \\{f_{0} - f_{7}} \\{f_{1} - f_{6}} \\{f_{2} - f_{5}} \\{f_{3} - f_{4}}\end{bmatrix}}} & (42)\end{matrix}$

By substituting figures expressed by an equation (43) for f₀+f₇, f₁+f₆,f₂+f₅, f₃+f₄, f₀−f₇, f₁−f₆, f₂−d₅ and f₃−f₄ contained in the equation(42) and then by changing the right side of the equation (42), anequation (44) can be obtained. By rearranging the equation (44), anequation (45) can be obtained. The 8-8 DCT/2-4-8 DCT device of the firstembodiment is adapted to perform the 8-8 DCT in accordance with theequation (45). $\begin{matrix}\left. \begin{matrix}{{a_{0} = {f_{0} + f_{7}}},\quad {a_{1} = {f_{1} + f_{6}}},\quad {a_{2} = {f_{2} + f_{5}}},\quad {a_{3} = {f_{3} + f_{4}}},} \\{{a_{4} = {f_{0} - f_{7}}},\quad {a_{5} = {f_{1} - f_{6}}},\quad {a_{6} = {f_{2} - f_{5}}},\quad {a_{7} = {f_{3} - f_{4}}}}\end{matrix} \right\} & (43) \\{\begin{bmatrix}F_{0} \\F_{2} \\F_{4} \\F_{6} \\F_{1} \\F_{3} \\F_{5} \\F_{7}\end{bmatrix} = {\begin{bmatrix}{a_{0} + a_{1} + a_{3} + a_{2}} & 0 & 0 & 0 & 0 & 0 & 0 \\0 & {a_{0} - a_{3}} & {a_{1} - a_{2}} & 0 & 0 & 0 & 0 \\{a_{0} - a_{1} + a_{3} - a_{2}} & 0 & 0 & 0 & 0 & 0 & 0 \\0 & {{- a_{1}} + a_{2}} & {a_{0} - a_{3}} & 0 & 0 & 0 & 0 \\0 & 0 & 0 & a_{4} & a_{5} & a_{6} & a_{7} \\0 & 0 & 0 & {- a_{6}} & a_{4} & {- a_{7}} & {- a_{5}} \\0 & 0 & 0 & {- a_{5}} & a_{7} & a_{4} & a_{6} \\0 & 0 & 0 & {- a_{7}} & a_{6} & {- a_{5}} & a_{4}\end{bmatrix}\begin{bmatrix}P_{3} \\P_{5} \\P_{1} \\P_{6} \\P_{4} \\P_{2} \\P_{0}\end{bmatrix}}} & (44) \\\left. \begin{matrix}{\begin{bmatrix}F_{0} \\F_{4} \\F_{2} \\F_{6}\end{bmatrix} = {\begin{bmatrix}{a_{0} + a_{1} + a_{3} + a_{2}} & 0 & 0 \\{a_{0} - a_{1} + a_{3} - a_{2}} & 0 & 0 \\0 & {a_{0} - a_{3}} & {a_{1} - a_{2}} \\0 & {{- a_{1}} - a_{2}} & {a_{0} - a_{3}}\end{bmatrix}\begin{bmatrix}P_{3} \\P_{5} \\P_{1}\end{bmatrix}}} \\{\begin{bmatrix}F_{1} \\F_{3} \\F_{5} \\F_{7}\end{bmatrix} = {\begin{bmatrix}a_{4} & a_{5} & a_{6} & a_{7} \\{- a_{6}} & a_{4} & {- a_{7}} & {- a_{5}} \\{- a_{5}} & a_{7} & a_{4} & a_{6} \\{- a_{7}} & a_{6} & {- a_{5}} & a_{4}\end{bmatrix}\begin{bmatrix}P_{6} \\P_{4} \\P_{2} \\P_{0}\end{bmatrix}}}\end{matrix} \right\} & (45)\end{matrix}$

Next, operational equations used to perform the 2-4-8 DCT on every oneline or one string of 8×8 picture element data are described below.

By expressing the two-dimensional equation (21) described in the above“Description of the Related Art” in the form of a one-dimensionalequation (46) and by setting F(0), F(1), F(2), F(3), F(4), F(5), F(6),F(7), f(0, z), f(1, z), f(2, z), f(3, z), f(4, z), f(5, z), f(6, z) andf(7, z) obtained by decompressing the equation (46) with respect to hand x so that F(0)=F₀, F(1)=F₁, F(2)=F₂, F(3)=F₃, F(4)=F₄, F(5)=F₅,F(6)=F₆ and F(7)=F₇, in the same manner as for the equation (40), andsetting so that f(0, z)=f₀, f(1, z)=f₁, f(2, z)=f₂, f(3, z)=f₃, f(4,z)=f₄, f(5, z)=f₅, f(6, z)=f₆, and f(7, z)=f₇, an equation (47) can beobtained. Values of P₀ to P6 in the equation (47) are the same as thosein the equation (40). $\begin{matrix}{\left. \begin{matrix}{{F(h)} = {{C(h)}{\sum\limits_{x = 0}^{7}{\left\{ {{f\left( {x,{2z}} \right)} + {f\left( {x,{{2z} + 1}} \right)}} \right\} \cos \quad \beta}}}} \\{{F\left( {h,{v + 4}} \right)} = {{C(h)}{\sum\limits_{x = 0}^{7}{\left\{ {{f\left( {x,{2z}} \right)} + {f\left( {x,{{2z} + 1}} \right)}} \right\} \cos \quad \beta}}}}\end{matrix} \right\} {{\text{where}\quad \beta} \equiv \frac{\pi \quad {h\left( {{2x} + 1} \right)}}{16}}} & (46) \\{\begin{bmatrix}F_{0} \\F_{1} \\F_{2} \\F_{3} \\F_{4} \\F_{5} \\F_{6} \\F_{7}\end{bmatrix} = {\begin{bmatrix}P_{3} & P_{3} & P_{3} & P_{3} & 0 & 0 & 0 & 0 \\P_{5} & P_{1} & {- P_{1}} & {- P_{5}} & 0 & 0 & 0 & 0 \\P_{3} & {- P_{3}} & {- P_{3}} & P_{3} & 0 & 0 & 0 & 0 \\P_{1} & {- P_{5}} & P_{5} & {- P_{1}} & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & P_{3} & P_{3} & P_{3} & P_{3} \\0 & 0 & 0 & 0 & P_{5} & P_{1} & {- P_{1}} & {- P_{5}} \\0 & 0 & 0 & 0 & P_{3} & {- P_{3}} & {- P_{3}} & P_{3} \\0 & 0 & 0 & 0 & P_{1} & {- P_{5}} & P_{5} & {- P_{1}}\end{bmatrix}\begin{bmatrix}{f_{0} + f_{1}} \\{f_{2} + f_{3}} \\{f_{4} + f_{5}} \\{f_{6} + f_{7}} \\{f_{0} - f_{1}} \\{f_{2} - f_{3}} \\{f_{4} - f_{5}} \\{f_{6} - f_{7}}\end{bmatrix}}} & (47)\end{matrix}$

By changing the right side of the equation (47), an equation (48) can beobtained. By rearranging the equation (48), an equation (49) can beobtained. $\begin{matrix}\left. \begin{matrix}{\begin{bmatrix}F_{0} \\F_{1} \\F_{2} \\F_{3}\end{bmatrix} = {\begin{bmatrix}{\left( {f_{0} + f_{1}} \right) + \left( {f_{2} + f_{3}} \right) + \left( {f_{4} + f_{5}} \right) + \left( {f_{6} + f_{7}} \right)} & 0 & 0 \\0 & {\left( {f_{0} + f_{1}} \right) - \left( {f_{6} + f_{7}} \right)} & {\left( {f_{2} + f_{3}} \right) - \left( {f_{4} + f_{5}} \right)} \\{\left( {f_{0} + f_{1}} \right) - \left( {f_{2} + f_{3}} \right) - \left( {f_{4} + f_{5}} \right) + \left( {f_{6} + f_{7}} \right)} & 0 & 0 \\0 & {{- \left( {f_{2} + f_{3}} \right)} + \left( {f_{4} + f_{5}} \right)} & {\left( {f_{0} + f_{1}} \right) - \left( {f_{6} + f_{7}} \right)}\end{bmatrix}\begin{bmatrix}P_{3} \\P_{5} \\P_{1}\end{bmatrix}}} \\{\begin{bmatrix}F_{4} \\F_{5} \\F_{6} \\F_{7}\end{bmatrix} = {\begin{bmatrix}{\left( {f_{0} - f_{1}} \right) + \left( {f_{2} - f_{3}} \right) + \left( {f_{4} - f_{5}} \right) + \left( {f_{6} - f_{7}} \right)} & 0 & 0 \\0 & {\left( {f_{0} - f_{1}} \right) - \left( {f_{6} - f_{7}} \right)} & {\left( {f_{2} - f_{3}} \right) - \left( {f_{4} - f_{5}} \right)} \\{\left( {f_{0} - f_{1}} \right) - \left( {f_{2} - f_{3}} \right) - \left( {f_{4} - f_{5}} \right) + \left( {f_{6} - f_{7}} \right)} & 0 & 0 \\0 & {{- \left( {f_{2} - f_{3}} \right)} + \left( {f_{4} - f_{5}} \right)} & {\left( {f_{0} - f_{1}} \right) - \left( {f_{6} - f_{7}} \right)}\end{bmatrix}\begin{bmatrix}P_{3} \\P_{5} \\P_{1}\end{bmatrix}}}\end{matrix} \right\} & (48) \\\left. \begin{matrix}{\begin{bmatrix}F_{0} \\F_{2} \\F_{1} \\F_{3}\end{bmatrix} = {\begin{bmatrix}{\left( {f_{0} + f_{1}} \right) + \left( {f_{2} + f_{3}} \right) + \left( {f_{4} + f_{5}} \right) + \left( {f_{6} + f_{7}} \right)} & 0 & 0 \\{\left( {f_{0} + f_{1}} \right) - \left( {f_{2} + f_{3}} \right) - \left( {f_{4} + f_{5}} \right) + \left( {f_{6} + f_{7}} \right)} & 0 & 0 \\0 & {\left( {f_{0} + f_{1}} \right) - \left( {f_{6} + f_{7}} \right)} & {\left( {f_{2} + f_{3}} \right) - \left( {f_{4} + f_{5}} \right)} \\0 & {{- \left( {f_{2} + f_{3}} \right)} + \left( {f_{4} + f_{5}} \right)} & {\left( {f_{0} + f_{1}} \right) - \left( {f_{6} + f_{7}} \right)}\end{bmatrix}\begin{bmatrix}P_{3} \\P_{5} \\P_{1}\end{bmatrix}}} \\{\begin{bmatrix}F_{4} \\F_{6} \\F_{5} \\F_{7}\end{bmatrix} = {\begin{bmatrix}{\left( {f_{0} - f_{1}} \right) + \left( {f_{2} - f_{3}} \right) + \left( {f_{4} - f_{5}} \right) + \left( {f_{6} - f_{7}} \right)} & 0 & 0 \\{\left( {f_{0} - f_{1}} \right) - \left( {f_{2} - f_{3}} \right) - \left( {f_{4} - f_{5}} \right) + \left( {f_{6} - f_{7}} \right)} & 0 & 0 \\0 & {\left( {f_{0} - f_{1}} \right) - \left( {f_{6} - f_{7}} \right)} & {\left( {f_{2} - f_{3}} \right) - \left( {f_{4} - f_{5}} \right)} \\0 & {{- \left( {f_{2} - f_{3}} \right)} + \left( {f_{4} - f_{5}} \right)} & {\left( {f_{0} - f_{1}} \right) - \left( {f_{6} - f_{7}} \right)}\end{bmatrix}\begin{bmatrix}P_{3} \\P_{5} \\P_{1}\end{bmatrix}}}\end{matrix} \right\} & (49)\end{matrix}$

By substituting figures expressed by an equation (50) for f₀+f₁, f₂+f₃,f₄+f₅, f₆+f₇, f₀−f₁, f₂−f₃, f₄−f₅ and f₆−f₇ contained in the equation(49), an equation (51) can be obtained. The 8-8 DCT/2-4-8 DCT device ofthe first embodiment is adapted to perform the 2-4-8 DCT in accordancewith the equation (51). $\begin{matrix}\left. \begin{matrix}{{b_{0} = {f_{0} + f_{1}}},\quad {b_{1} = {f_{2} + f_{3}}},\quad {b_{2} = {f_{4} + f_{5}}},\quad {b_{3} = {f_{6} + f_{7}}},} \\{{b_{4} = {f_{0} - f_{1}}},\quad {b_{5} = {f_{2} - f_{3}}},\quad {b_{6} = {f_{4} - f_{5}}},\quad {b_{7} = {f_{6} - f_{7}}}}\end{matrix} \right\} & (50) \\\left. \begin{matrix}{\begin{bmatrix}F_{0} \\F_{2} \\F_{1} \\F_{3}\end{bmatrix} = {\begin{bmatrix}{b_{0} + b_{1} + b_{3} + b_{2}} & 0 & 0 \\{b_{0} - b_{1} + b_{3} - b_{2}} & 0 & 0 \\0 & {b_{0} - b_{3}} & {b_{1} - b_{2}} \\0 & {{- b_{1}} + b_{2}} & {b_{0} - b_{3}}\end{bmatrix}\begin{bmatrix}P_{3} \\P_{5} \\P_{1}\end{bmatrix}}} \\{\begin{bmatrix}F_{4} \\F_{6} \\F_{5} \\F_{7}\end{bmatrix} = {\begin{bmatrix}{b_{4} + b_{5} + b_{7} + b_{6}} & 0 & 0 \\{b_{4} - b_{5} + b_{7} - b_{6}} & 0 & 0 \\0 & {b_{4} - b_{7}} & {b_{5} - b_{6}} \\0 & {{- b_{5}} + b_{6}} & {b_{4} - b_{7}}\end{bmatrix}\begin{bmatrix}P_{3} \\P_{5} \\P_{1}\end{bmatrix}}}\end{matrix} \right\} & (51)\end{matrix}$

The 8-8 DCT/2-4-8 DCT described above is composed of a multiplexer 12,eight data registers 14, to 148 constituting a first data register group13, four adding circuits 18, to 184 constituting a first adding circuitgroup 17, four subtracting circuits 20 ₁ to 20 ₄ constituting asubtracting circuit group 19, eight data registers 22 ₁ to 22 ₈constituting a second data register group 21, eight multiplexers 24 ₁ to24 ₈ constituting a first multiplexer group 23, two adding/subtractingcircuits 26 ₁ and 26 ₂ constituting a first adding/subtracting circuitgroup 25, two multiplexers 28 ₁ to 28 ₂ constituting a secondmultiplexer group 27, seven data registers 30 ₁ to 30 ₇ constituting athird data register group 29, a P₃ coefficient multiplying circuit 32 ₁,a P₅ coefficient multiplying circuit 32 ₂, a P₁ coefficient multiplyingcircuit 32 ₃, a P₆/P₃ coefficient multiplying circuit 32 ₄, a P₄/P₅coefficient multiplying circuit 32 ₅, P₂ coefficient multiplying circuit32 ₆, a P₀/P₁ coefficient multiplying circuit 32 ₇, saven data registers34 ₁ to 34 ₇ constituting a fourth data register group 33, five ANDcircuits 36 ₁ to 36 ₅, four adding circuits 38 ₁ to 38 ₄ constituting asecond adding circuit group 37 and five data registers 40 ₁, to 40 ₅constituting a fifth data register group 39. Hereinafter, the dataregister is referred simply to as a register (shown as “REG” in figures)and the multiplexer simply to a MUX.

The MUX 12 outputs selectively eight pieces of picture element datacontained in each of lines constituting an 8×8 picture element block onwhich a primary DCT is performed or eight pieces of picture element datacontained in each of strings constituting 8×8 data block obtained by theprimary DCT. Each of eight pieces of data output from the MUX 12 isreferred to by f₀ to f₇. When the 8-8 DCT is performed, the MUX 12stores data f₀ into the register 14 ₁, data f₇ into the register 14 ₂,data f₁ into the register 14 ₃, data f₆ into the register 14 ₄, data f₂into the register 14 ₅, data f₅ into the register 14 ₆, data f₃ into theregister 14 ₇ and data f₄ into the register 14 ₈ in the first registergroup 13 and, when the 2-4-8 DCT is performed, the MUX 12 stores data f₁to f₈ into the register 14 ₁ to 14 ₈ which correspond to the data f₁ tof₈.

Each of the four adding circuits 18 ₁ to 18 ₄ constituting the firstadding circuit group 17, in the case of both the 8-8 DCT and 2-4-8 DCT,performs adding operations on data output from two registers. That is,the adding circuit 18 ₁ adds data stored in the register 14 ₁ to datastored in the register 14 ₂. The adding circuit 18 ₂ adds data stored inthe register 14 ₃ to data stored in the register 14 ₄. The addingcircuit 18 ₃ adds data stored in the register 14 ₅ to data stored in theregister 14 ₆. The adding circuit 18 ₄ adds data stored in the register14 ₇ to data stored in the register 14 ₈.

Each of the four subtracting circuit 20 ₁ to 20 ₄ constituting thesubtracting circuit group 19, in the case of both the 8-8 DCT and 2-4-8DCT, performs subtracting operations on data output from two registers.That is, the subtracting circuit 20 ₁ subtracts data stored in theregister 14 ₂ from data stored in the register 14 ₁. The subtractingcircuit 20 ₂ subtracts data stored in the register 14 ₃ from data storedin the register 14 ₄. The subtracting circuit 20 ₃ subtracts data storedin the register 14 ₆ from data stored in the register 14 ₅. Thesubtracting circuit 20 ₄ subtracts data stored in the register 14 ₈ fromdata stored in the register 14 ₇.

Each of the registers 22 ₁ to 22 ₈ constituting the second registergroup 21 temporarily stores data output from each of the adding circuits18 ₁ to 18 ₄ or data output from each of the subtracting circuits 20 ₁to 20 ₄. The registers 22 ₁ temporarily stores data output from theadding circuit 18 ₁. The register 22 ₂ temporarily stores data outputfrom the adding circuit 18 ₂. The register 22 ₃ temporarily stores dataoutput from the adding circuit 18 ₃. The register 22 ₄ temporarilystores data output from the adding circuit 18 ₄. The register 22 ₅temporarily stores data output from the subtracting circuit 20 ₁. Theregister 22 ₆ temporarily stores data output from the subtractingcircuit 20 ₂. The register 22 ₇ temporarily stores data output from thesubtracting circuit 20 ₃. The register 22 ₈ temporarily stores dataoutput from the subtracting circuit 20 ₄. The MUX 12 and each of theregisters 14 ₁ to 14 ₈, of the adding circuits 18 ₁ to 18 ₄, each of thesubtracting circuits 20 ₁ to 20 ₄ and each of the registers 22 ₁ to 22 ₈repeat the same operations for every four operation cycles and each ofthe operation cycles corresponds to four operation cycles performed bythe MUXs 24 ₁ to 24 ₈ and thereafter.

An operation of selecting data performed by each of the MUXs 24 ₁, 24 ₂,24 ₃ and 24 ₄ constituting a first MUX group 23 is the same in both the8-8 DCT and 2-4-8 DCT. That is, the MUX 24 ₁ is connected to an outputof each of the registers 22 ₁, 22 ₂, 22 ₃ and 22 ₄ and is adapted toselect the register in the order of the registers 22 ₁, 22 ₄, 22 ₁ and22 ₄ and to output four pieces of data sequentially. The MUX 24 ₂ isconnected to outputs of the registers 22 ₁, 22 ₂, 22 ₃ and 22 ₄ and isadapted to select the register in the order of the registers 22 ₂, 22 ₃,22 ₂ and 22 ₃ and to output four pieces of data sequentially. The MUX 24₃ is connected to outputs of the registers 22 ₁, 22 ₂, 22 ₃ and 22 ₄ andis adapted to select the register in the order of the registers 22 ₁, 22₄, 22 ₂ and 22 ₃ and to output four pieces of data sequentially. The MUX24 ₄ is connected to outputs of the registers 22 ₁, 22 ₂, 22 ₃ and 22 ₄and is adapted to select the register in the order of the registers 22₂, 22 ₃, 22 ₁ and 22 ₂ and to output four pieces of data sequentially.

An operation of selecting data of each of MUX 24 ₅, MUX 24 ₆, MUX 24 ₇and MUX 24 ₈ constituting the first MUX group 23 is different in betweenthe 8-8 DCT and 2-4-8 DCT.

The operation of selecting data of each of the MUX 24 ₅, MUX 24 ₆, MUX24 ₇ and MUX 24 ₈ in the case of the 8-8 DCT is as follows. The MUX 24 ₅is connected to outputs of the registers 22 ₅, 22 ₆, 22 ₇ and 22 ₈ andis adapted to select the register in the order of the registers 22 ₅, 22₇, 22 ₆ and 22 ₈ and to output four pieces of data sequentially. The MUX24 ₆ is connected to outputs of the registers 22 ₅, 22 ₆, 22 ₇ and 22 ₈and is adapted to select the register in the order of the registers 22₆, 22 ₅, 22 ₈ and 22 ₇ and to output four pieces of data sequentially.The MUX 24 ₇ is connected to outputs of the registers 22 ₅, 22 ₆, 22 ₇and 22 ₈ and is adapted to select the register in the order of theregisters 22 ₇, 22 ₈, 22 ₅ and 22 ₆ and to output four pieces of datasequentially. The MUX₈ is connected to outputs of the registers 22 ₅, 22₆, 22 ₇ and 22 ₈ and is adapted to select the register in the order ofthe registers 22 ₈, 22 ₆, 22 ₇ and 22 ₅ and to output four pieces ofdata sequentially.

The operation of selecting data of each of the MUX 24 ₅, MUX 24 ₆, MUX24 ₇ and MUX 24 ₈ in the case of the 2-4-8 DCT is as follows. The MUX 24₅ is connected to outputs of the registers 22 ₅, 22 ₆, 22 ₇ and 22 ₈ andis adapted to select the register in the order of the registers 22 ₅, 22₈, 22 ₅ and 22 ₈ and to output four pieces of data sequentially. The MUX24 ₆ is connected to outputs of the registers 22 ₅, 22 ₆, 22 ₇ and 22 ₈and is adapted to select the register in the order of the registers 22₅, 22 ₈, 22 ₆ and 22 ₇ and to output four pieces of data sequentially.The MUX 24 ₇ is connected to outputs of the registers 22 ₅, 22 ₆, 22 ₇and 22 ₈ and is adapted to select the register in the order of theregisters 22 ₆, 22 ₇, 22 ₆ and 22 ₇ and to output four pieces of datasequentially. The MUX 24 ₈ is connected to outputs of the registers 22₅, 22 ₆, 22 ₇ and 22 ₈ and is adapted to select the register in theorder of the registers 22 ₆, 22 ₇, 22 ₅ and 22 ₈ and to output fourpieces of data sequentially.

The adding/subtracting circuit 26 ₁ constituting a firstadding/subtracting group 25, in the case of both the 8-8 DCT and the2-4-8 DCT, performs adding operations on data output in a first orderand second order out of four pieces of data output from the MUX 24 ₁ andon data output in the first order and second order out of four pieces ofdata output from the MUX 24 ₂, respectively and performs subtractingoperations on data output in a third order and fourth order out of thefour pieces of data output from the MUX 24 ₁ and on data output in thethird order and fourth order out of the four pieces of data output fromthe MUX 24 ₂. That is, data output in the first order from the MUX 24 ₁is added to data output in the first order from the MUX 24 ₂ and thesame adding operations are performed on the data output in the secondorder. In the subtracting operations to be performed by theadding/subtracting circuit 26 ₁, data output from the MUX 24 ₂ issubtracted from data output from the MUX 24 ₁. The adding/subtractingcircuit 26 ₂, in the case of the 2-4-8 DCT, performs adding operationson data output in the first order and second order out of four pieces ofdata output from MUX 24 ₅ and on data output in the first order andsecond order out of the four pieces of data output from MUX 24 ₇ andperforms subtracting operations on data output in the third order andfourth order out of four pieces of data output from the MUX 24 ₅ and ondata output in the third order and fourth order out of the four piecesof data output from the MUX 24 ₇. In the subtracting operations to beperformed by the adding/subtracting circuit 26 ₂, data output from theMUX 24 ₇ is subtracted from data output from the MUX 24 ₅.

The MUX 28 ₁ constituting the second MUX group 27, in the case of the8-8 DCT, selects four pieces of data output sequentially from the MUX 24₅ and, in the case of the 2-4-8 DCT, selects data output sequentiallyfrom the adding/subtracting circuit 26 ₂. The MUX 28 ₂, in the case ofthe 8-8 DCT, selects four pieces of data output sequentially from theMUX 24 ₇ and, in the case of the 2-4-8 DCT, does not select four piecesof data output from the MUX 24 ₇ but selects “0” four times whichcorresponds to four operation cycles of the MUX 28 ₂ (the operationcycle in the 2-4-8 DCT is called a “second operation cycle”).

The register 30 ₁ constituting the third register group 29 sequentiallystores four pieces of data on arithmetic operation results. The register30 ₂ sequentially stores four pieces of data output sequentially fromthe MUX 24 ₃. The register 30 ₃ sequentially stores four pieces of dataoutput sequentially from the MUX 24 ₄. The register 30 ₄ sequentiallystores four pieces of data output sequentially from the MUX 28 ₁. Theregister 30 ₅ sequentially stores four pieces of data outputsequentially from the MUX 24 ₆. The register 30 ₆ sequentially storesfour pieces of data output sequentially from the MUX 28 ₂. The register30 ₇ sequentially stores four pieces of data output sequentially fromthe MUX 24 ₈.

The P₃ coefficient multiplying circuit 32 ₁ multiplies each of fourpieces of data output sequentially from the register 30 ₁ by a fixedcoefficient P₃. The P₅ coefficient multiplying circuit 32 ₂ multiplieseach of four pieces of data output sequentially from the register 30 ₂by a fixed coefficient P₅. The P₁ coefficient multiplying circuit 32 ₃multiplies each of four pieces of data output sequentially from theregister 30 ₃ by a fixed coefficient P₅. The P₆/P₃ coefficientmultiplying circuit 32 ₄ switches fixed coefficients between the 8-8 DCTand the 2-4-8 DCT and, in the case of the 8-8 DCT, multiplies each offour pieces of data output from the register 30 ₄ by a fixed coefficientP₆ and, in the case of the 2-4-8 DCT, multiplies each of four pieces ofdata output from the register 30 ₄ by a fixed coefficient P₃. The P₄/P₅coefficient multiplying circuit 32 ₅ switches fixed coefficients betweenthe 8-8 DCT and the 2-4-8 DCT and, in the case of the 8-8 DCT,multiplies each of four pieces of data output from the register 30 ₅ bya fixed coefficient P₄ and, in the case of the 2-4-8 DCT, multiplieseach of four pieces of data output from the register 30 ₅ by a fixedcoefficient P₅. The P₂ coefficient multiplying circuit 32 ₆ multiplieseach of four pieces of data output sequentially from the register 30 ₆by a fixed coefficient P₂. The P₀P₁ coefficient multiplying circuit 32 ₇switches fixed coefficients between the 8-8 DCT and the 2-4-8 DCT and,in the case of the 8-8 DCT, multiplies each of four pieces of dataoutput from the register 30 ₇ by a fixed coefficient P₀ and, in the caseof the 2-4-8 DCT, multiplies each of four pieces of data output from theregister 30 ₇ by a fixed coefficient P₁.

The register 34 ₁ constituting the fourth register group 33, in both the8-6 DCT and 2-4-8 DCT, stores, in order, each of four pieces of dataoutput sequentially from the P₃ coefficient multiplying circuit 32 ₁ andoutputs each data as a positive value. The register 34 ₂, in both the8-8 DCT and the 2-4-8 DCT, stores each of four pieces of data outputsequentially from the P₅ coefficient circuit 74 and outputs data to beoutput in a first order and fourth order as positive values and data tobe output in a second order and third order as negative values. Theregister 34 ₃, in both the 8-8 DCT and the 2-4-8 DCT, sequentiallystores each of four pieces of data output, in order, from the P₁coefficient circuit 32 ₃ and outputs data to be output in a first orderand third order as positive values and data to be output in a secondorder and fourth order as negative values.

The register 34 ₄ stores, in order, each of four pieces of data outputsequentially from the P₆/P₃ coefficient multiplying circuit 32 ₄ andoutputs, in the case of the 8-8 DCT, data to be output in a first orderas a positive value and data to be output in a second order to fourthorder as negative values, and in the case of the 2-4-8 DCT, each of thefour pieces of data to be output in a first order to fourth order as apositive value. The register 34 ₅ stores, in order, each of four piecesof data output sequentially from the P₄/P₅ coefficient multiplyingcircuit 32 ₅ and outputs, in the case of the 8-8 DCT, data to be outputin a first order to fourth order as positive values and, in the case ofthe 2-4-8 DCT, each of the four pieces of data to be output in a firstorder and fourth order as positive values and data to be output in asecond order and third order as negative values. The register 34 ₆stores, in order, each of four pieces of data output sequentially fromthe P₂ coefficient multiplying circuit 32 ₆, outputs data to be outputin the first order and third order as positive values and data to beoutput in the second order and fourth order as negative values. Theregister 34 ₇ stores, in order, each of four pieces of data outputsequentially from the P₀/P₁ multiplying circuit 32 ₇ and, in the case ofthe 8-8 DCT, outputs data to be output in a first order and fourth orderas positive values and data to be output in the second order and thirdorder as negative orders and, in the case of the 2-4-8 DCT, outputs datato be output in a first order and third order as positive values anddata to be output in a second order and fourth order as negative values.

The adding circuit 38 ₁ contained in the second adding circuit group 37constitutes an accumulative circuit for data together with the register40 ₁ contained in the fifth register group 39 and with the AND circuit36 ₁. In both the 8-8 DCT and the 2-4-8 DCT, to one input of the ANDcircuit 36 ₁ is fed data from the register 40 ₁ and, to the other inputof the AND circuit 36 ₁ are fed signals “0”, “1”, “0” and “1”sequentially in every operation cycle in the order of a first operationcycle to a fourth operation cycle out of four operation cycles, whichare output from a binary signal string generating circuit (not shown).That is, an accumulative value is output from the register 40 ₁ which isobtained by adding, in the adding circuit 38 ₁, data output from theregister 34 ₁ and fed to one input of the adding circuit 38 ₁ to datastored in the register 40 ₁ on one previous clock and fed to the otherinput of the adding circuit 38 ₁ through the AND circuit 36 ₁ on thenext clock.

The adding circuit 38 ₂ constitutes an accumulative circuit for datatogether with the register 40 ₂ and with the AND circuit 36 ₂. Also, inboth the case of the 8-8 DCT and the 2-4-8 DCT, to one input of the ANDcircuit 36 ₂ is fed data from the register 40 ₂ and to the other inputof the AND circuit 36 ₂ are fed signals “0”, “1”, “0” and “1”sequentially in every operation cycle in the order of a first operationcycle to a fourth operation cycle out of four operation cycles, whichare output from a binary signal string generating circuit (not shown).That is, an accumulative value is output from the register 40 ₂ which isobtained by adding, in the adding circuit 38 ₂, data output from theregister 34 ₄ and the register 34 ₃ and fed to a first input and secondinput of the adding circuit 38 ₂ to data stored in the register 40 ₂ onone previous clock and fed, on the next clock, to a third input of theadding circuit 38 ₂ through the AND circuit 36 ₂.

The adding circuit 38 ₃ constitutes an accumulative circuit for datatogether with the register 40 ₃ and with the AND circuit 36 ₃. In thecase of the 8-8 DCT, to one input of the AND circuit 36 ₃ is fed datafrom the register 34 ₃ and to the other input of the AND circuit 36 ₃ isfed a “0” signal in every operation cycle in the order of a firstoperation cycle to a fourth operation cycle out of four operationcycles. In the case of the 2-4-8 DCT, to one input of the AND circuit 36₃ is fed data from the register 34 ₃ and to the other input of the ANDcircuit 36 ₃ are fed signals “0”, “1”, “0” and “1” sequentially in everyoperation cycle in the order of a first operation cycle to a fouroperation cycle out of four second operation cycles, which are outputfrom a binary signal string generating circuit (not shown). That is, inthe case of the 8-8 DCT, data from the register 34 ₂ passes by theadding circuit 38 ₃ and is stored in the register 40 ₃. In the case ofthe 2-4-8 DCT, an accumulative value is output from the register 40 ₃,which is obtained by adding, in the adding circuit 38 ₃, data outputfrom the register 34 ₂ and fed to one input of the adding circuit 38 ₃to data stored in the register 40 ₃ on one previous clock and fed to theother input of the adding circuit 38 ₃ through the AND circuit 36 ₃ onthe next clock.

The adding circuit 38 ₄ constitutes an accumulative circuit for datatogether with the register 40 ₄ and with the AND circuit 36 ₄ and ANDcircuit 36 ₅. To one input of the AND circuit 36 ₄ is fed data from theregister 34 ₄ and, in the case of the 8-8 DCT, to the other input of theAND circuit 36 ₄ is fed a “1” signal in every operation cycle from afirst operation cycle to fourth operation cycle out of four operationcycles and, in the case of the 2-4-8 DCT, are fed signals “0” in everyoperation cycle in the order of a first operation cycle to fourthoperation cycle out of four second operation cycles, which is outputfrom a binary signal string generating circuit (not shown). To one inputof the AND circuit 36 ₅ is fed data from the register 40 ₄ and, in thecase of the 8-8 DCT, to the other input of the AND circuit 36 ₅ is fed a“0” signal in every operation cycle from a first operation cycle to afourth operation cycle out of four operation cycles and, in the case ofthe 2-4-8 DCT, are fed signals “0”, “1”, “0” and “1” in every operationcycle in the order of a first operation cycle to a fourth operationcycle out of four second operation cycles, which is output from a binarysignal string generating circuit (not shown).

In the case of the 8-8 DCT, each of data output sequentially in everyoperation cycle from the registers 34 ₄, 34 ₅, 34 ₆ and 34 ₇ is input toa first input, second input, third input and fourth input of the addingcircuit 38 ₄ in every operation cycle, is added and stored in theregister 40 ₄ in order and, in the case of the 2-4-8 DCT, an accumulatedvalue is output from the register 40 ₄, which is obtained by adding, inthe adding circuit 38 ₄, data output sequentially from the registers 34₅, 34 ₆ and 34 ₇ in every operation cycle and fed to a second input,third input and fourth input of the adding circuit 38 ₄ to data storedin the register 40 ₅ on one previous clock and fed, on the next clock,to a fifth input of the adding circuit 38 ₄ through the AND circuit 36₄.

Though delays in each circuit of the MUX 12 to the register 40 ₁ toregister 40 ₄ and deviations in their operation cycles occur, in thefollowing description of operations, such delays and deviations will notbe mentioned in detail.

Next, operations in the first embodiment will be described by referringto FIGS. 1 to 4. First, operations for the 8-8 DCT will be explained.

Each of eight pieces of picture element data f₀ to f₇ contained in eachline constituting the 8×8 picture element data block, outputsequentially from the MUX 12, is stored into each of registers 14 ₁ to14 ₈ constituting the first register group 13. That is, data f₀ isstored in the register 14 ₁, data f₇ in the register 14 ₂, data f₁ inthe register 14 ₃, data f₆ in the register 14 ₄, data f₂ in the register14 ₅, data f₅ in the register 14 ₆, data f₃ in the register 14 ₇ anddata f₄ in the register 14 ₈. The data f₀ stored in the register 14 ₁ isfed to a summand input of the adding circuit 18 ₁ and data f₇ stored inthe register 14 ₂ is fed to an addend input of the adding circuit 18 ₁and then data f₀+f₇=a₀ is output from the adding circuit 18 ₁. The dataf₁ stored in the register 14 ₃ is fed to a summand input of the addingcircuit 18 ₂ and the data f₆ stored in the register 14 ₄ is fed to anaddend input of the adding circuit 18 ₂ and then an added value f₁+f₆=a₁is output from the adding circuit 18 ₂. The data f₂ stored in theregister 14 ₅ is fed to a summand input of the adding circuit 18 ₃ andthe data f₅ stored in the register 14 ₆ is fed to an addend input of theadding circuit 18 ₃ and then data f₂+f₅=a₂ is output from the addingcircuit 18 ₃. The data f₃ stored in the register 14 ₇ is fed to asummand input of the adding circuit 18 ₄ and the data f₄ stored in theregister 14 ₇ and then data f₃+f₄=a₃ is output from the adding circuit18 ₄. The data f₀ stored in the register 14 ₁ is fed to a minuend inputof the subtracting circuit 20 ₁ and data f₇ stored in the register 14 ₂is fed to a subtrahend input of the subtracting circuit 20 ₁ and thendata f₀−f₇=a₄ is output from the subtracting circuit 20 ₁. The data f₁stored in the register 14 ₃ is fed to a minuend input of the subtractingcircuit 20 ₂ and data f₆ stored in the register 14 ₄ is fed to asubtrahend input of the subtracting circuit 20 ₂ and then data f₁−f₆=a₅is output from the subtracting circuit 20 ₂. The data f₂ stored in theregister 14 ₅ is fed to a minuend input of the subtracting circuit 20 ₃and data f₅ stored in the register 14 ₆ is fed to a subtrahend input ofthe subtracting circuit 20 ₃ and then data f₂−f₅=a₆ is output from thesubtracting circuit 20 ₃. The data f₃ stored in the register 14 ₇ is fedto a minuend input of the subtracting circuit 20 ₄ and data f₄ stored inthe register 14 ₇ is fed to a subtrahend input of the subtractingcircuit 20 ₄ and then data f₃−f₄=a₄ is output from the subtractingcircuit 20 ₄.

Data a₀ to a₃ output from the adding circuit 18 ₁ to adding circuit 18 ₄are input into the MUX 24 ₁ to MUX 24 ₄ through the register 22 ₁ toregister 22 ₄. The MUX 24 ₁ selects the registers in the order of theregister 22 ₁, 22 ₄, 22 ₁ and 22 ₄ and outputs sequentially four piecesof corresponding data a₀, a₃, a₀ and a₃. The MUX 24 ₂ selects theregisters in the order of the register 22 ₂, 22 ₃, 22 ₃ and 22 ₃ andoutputs sequentially four pieces of corresponding data a₁, a₂, a₁ anda₂. The MUX 24 ₃ selects the registers in the order of the register 22₁, 22 ₄, 22 ₂ and 22 ₃ and outputs sequentially four pieces ofcorresponding data a₀, a₃, a₁ and a₂. The MUX 24 ₄ selects the registersin the order of the register 22 ₂, 22 ₃, 22 ₁ and 22 ₄ and outputssequentially four pieces of corresponding data a₁, a₂, a₀ and a₃.

The MUX 24 ₅ selects the registers in the order of the register 22 ₅, 22₇, 22 ₆ and 22 ₈ and outputs sequentially four pieces of correspondingdata a₄, a₆, a₅and a₇. The MUX 24 ₆ selects the registers in the orderof the register 22 ₆, 22 ₅, 22 ₈ and 22 ₇ and outputs sequentially fourpieces of corresponding data a₅, a₄, a₇ and a₆. The MUX 24 ₇ selects theregisters in the order of the register 22 ₇, 22 ₈, 22 ₅ and 22 ₆ andoutputs sequentially four pieces of corresponding data a₆, a₇, a₄ anda₅. The MUX 24 ₈ selects the registers in the order of the register 22₈, 22 ₆, 22 ₇ and 22 ₅ and outputs sequentially four pieces ofcorresponding data a₇, a₅, a₆ and a₄.

The adding/subtracting circuit 26 ₁ performs adding operations on dataoutput in the first order and second order out of four pieces of dataa₀, a₂, a₀ and a₃ output sequentially from the MUX 24 ₁ and on dataoutput in the first order and second order out of four pieces of dataa₁, a₂, a₁ and a₂ output from the MUX 24 ₂ and performs subtractingoperations on data output in the third order and fourth order out offour pieces of data a₀, a₂, a₀ and a₃ output sequentially from the MUX24 ₁ and on data output in the third order and fourth order out of fourpieces of data a₁, a₂, a₁ and a₂ output from the MUX 24 ₂ and, as aresult, outputs data a₀+a₁, data a₃+a₂, data a₀−a₁ and data a₃−a₂sequentially. That is, data output in the first order from the MUX 24 ₁is added to data output in the first order from the MUX 24 ₂ and thesame adding operations are performed on the data output in the secondorder and further the similar subtracting operations are performed onthe data output in the third and fourth order. Each of the data a₀+a₁,a₃+a₂, a₀−a₁ and a₃−a₂ output in every operation cycle from a firstoperation cycle to fourth operation cycle out of four operation cyclesfrom the adding/subtracting circuit 26 ₁, after being storedsequentially into the register 30 ₁ (see the register 30 ₁ shown in FIG.3), is multiplied by the fixed coefficient P₃ in the P₃ coefficientmultiplying circuit 32 ₁ and stored, in order, into the register 34 ₁(see the register 34 ₁ in FIG. 3). Each of the data a₀, a₃, a₁ and a₂output sequentially from the MUX 24 ₃, after being stored sequentiallyinto the register 30 ₂ (see the register 30 ₂ shown in FIG. 3), ismultiplied by the fixed coefficient P₅ in the P₅ coefficient multiplyingcircuit 32 ₂ and stored sequentially into the register 34 ₂ (see theregister 34 ₁ in FIG. 3). Each of the data a₁, a₂, a₀ and a₃ outputsequentially from the MUX 24 ₄, after being stored sequentially into theregister 30 ₃ (see the register 30 ₃ shown in FIG. 3), is multiplied bythe fixed coefficient P₁ in the P₁ coefficient multiplying circuit 32 ₃and stored sequentially into the register 34 ₃ (see the register 34 ₃ inFIG. 3).

Each of the data a₄, a₆, a₅ and a₇ output, in order, from the MUX 24 ₅,after being stored sequentially into the register 30 ₄ (see the register30 ₄ shown in FIG. 4), is multiplied by the fixed coefficient P₆ in theP₆/P₃ coefficient multiplying circuit 32 ₄ and stored sequentially intothe register 34 ₄ (see the register 34 ₄ in FIG. 4). Each of the dataa₅, a₄, a₇ and a₆ output, in order, from the MUX 24 ₆, after beingstored sequentially into the register 30 ₅ (see the register 30 ₅ shownin FIG. 4), is multiplied by the fixed coefficient P₄ in the P₄/P₅coefficient multiplying circuit 32 ₅ and stored sequentially into theregister 34 ₅ (see the register 34 ₅ in FIG. 3). Each of the data a₆,a₇, a₄ and a₅ output, in order, from the MUX 24 ₇, after being storedsequentially into the register 30 ₆ (see the register 30 ₆ shown in FIG.4), is multiplied by the fixed coefficient P₂ by the P₂ coefficientmultiplying circuit 32 ₆ and stored sequentially into the register 34 ₆(see the register 34 ₆ in FIG. 4). Each of the data a₇, a₅, a₆ and a₄output, in order, from the MUX 24 ₈ after being stored sequentially intothe register 30 ₇ (see the register 30 ₇ shown in FIG. 4), is multipliedby the fixed coefficient P₀ by the P₀/P₁ coefficient multiplying circuit32 ₇ and stored sequentially into the register 34 ₇ (see the register 34₇ in FIG. 4).

Out of data (a₀+a₁) P₃, data (a₃+a₂) P₃, data (a₀−a₁) P₃, data (a₃−a₂)P₃ output from the register 34 ₁ in every operation cycle from a firstoperation cycle to a fourth operation cycle out of the four operationcycles, the data (a₀+a₁) P₃ is stored into the register 40 ₁ in a firstoperation cycle out of four operation cycles performed by the addingcircuit 38 ₁, register 40 ₁ and AND circuit 36 ₁, data (a₀+a₁)P₃+(a₃+a₂) P₃ is stored into the register 40 ₁ in a second operationcycle, data (a₀−a₁) P₃ is stored into the register 40 ₁ in a thirdoperation cycle and data (a₀−a₁) P₃+(a₃−a₂) P₃ is registered into theregister 40 ₁ in a fourth operation cycle (see the register 40 ₁ in FIG.3). Of data stored sequentially into the register 40 ₁ and outputtherefrom, the data (a₀+a₁) P₃ stored in the first operation cycle andthe data (a₀−a₁) P₃ stored into the register 40 ₁ in the third operationcycle are undefined values and are not used, as transformationcoefficient data, in the discrete cosine transformation. The above dataare indicated with asterisks (*) on a lower right side of the outputline of the register 40 ₁ in FIG. 2.

The data (a₀+a₁) P₃+(a₃+a₂) P₃ stored in the second operation cycle andthe data (a₀−a₁) P₃+(a₃−a₂) P₃ stored in the fourth operation cycle areused as the transformation coefficient data F₀ and F₄ of operationvalues contained in the equation (45). The transformation coefficientdata F₀ and F₄ are shown on the lower right side of the output line ofthe register 40 ₁ in FIG. 2.

Out of data a₀P₅, data a₃P₅, data a₁P₅, data a₂P₅ output from theregister 34 ₂ in every operation cycle from a first operation cycle to afourth operation cycle out of the four operation cycles and data a₁P₁,data a₂P₁, data a₀P₁, data a₃P₁ output from the register 34 ₃ in everyoperation cycle from a first operation cycle to a fourth operation cycleout of the four operation cycles, the data a₀P₅+a₁P₁ are stored into theregister 40 ₂ in a first operation cycle out of four second operationcycles performed by the adding circuit 38 ₂, register 40 ₂ and ANDcircuit 36 ₂, the data a₀P₅+a₁P₁−a₃P₅−a₂P₁ are stored into the register40 ₉ in a second operation cycle, the data −a₂P₁+a₀P₁ are stored intothe register 40 ₂ in a third operation cycle and the data−a₁P₅+a₀P₁+a₂P₅−a₃P₁ are stored into the register 40 ₂ in the fourthcycle (see the register 40 ₂ in FIG. 3).

Of data stored sequentially into the register 40 ₂ and output therefrom,the data a₀P₅+a₁P₁ and the data a₀P₁−a₁P₅ stored in the first operationcycle and third operation cycle are undefined values and are not used,as transformation coefficient data, in the discrete cosinetransformation. The above data are indicated with asterisks (*) on alower right side of the output line of the register 40 ₂ in FIG. 2. Thedata a₀P₅+a₁P₁−a₃P₅−a₂P₁ and the data −a₁P₅+a₀P₁+a₂P₅−a₃P₁ stored in thesecond operation cycle and fourth operation cycle are used as thetransformation coefficient data F₂ and transformation coefficient dataF₆ of operation values contained in the equation (45). Thetransformation coefficient data F₂ and F₆ are shown on the lower rightside of the output line of the register 40 ₂.

Data a₄P₆, data −a₆P₆, data −a₅P₆, data −a₇P₆ output from the register34 ₄ in every operation cycle from a first operation cycle to a fourthoperation cycle out of the four operation cycles, since signals “0” arefed to other input of the AND circuit 36 ₃ in every operation cycle fromthe first operation cycle to the fourth operation cycle out of the fouroperation cycles, pass by the adding circuit 38 ₃ and are stored in theregister 40 ₃. Any data stored sequentially into the register 40 ₃ inevery operation cycle from the first operation cycle to the fourthoperation cycle out of the four operation cycles is an undefined valueand is not used, as transformation coefficient data, in the discretecosine transformation. The above data are indicated with asterisks (*)on a lower right side of the output line of the register 40 ₃ in FIG. 2.

Data a₄P₆, data −a₆P₆, data −a₅P₆, and data −a₇P₆ output sequentiallyfrom the register 34 ₄ in every operation cycle from the first operationcycle to the fourth operation cycle out of the four operation cycles andfed through the AND circuit 36 ₄, data a₅P₄, data a₄P₄, data a₇P₄, anddata a₆P₄ output from the register 34 ₅ in every operation cycle fromthe first operation cycle to the fourth operation cycle out of the fouroperation cycles, data a₆P₂, data −a₇P₂, data a₄P₂, and data −a₅P₂output from the register 34 ₆ in every operation cycle from the firstoperation cycle to the fourth operation cycle out of the four operationcycles, data a₇P₀, data −a₅P₀, data a₆P₀, and data a₄P₀ output from theregister 34 ₇ in every operation cycle from the first operation cycle tothe fourth operation cycle out of the four operation cycles, are added,in the adding circuit 38 ₄, by every operation cycle from the firstoperation cycle to fourth operation cycle out of the four operationcycles and the results of the adding operation are stored sequentiallyinto the register 40 ₄ (see the register 40 ₄ in FIG. 4).

Data a₄P₆+a₅P₄+a₆P₂+a₇P₀ stored in the register 40 ₄ and output in thefirst operation cycle out of the four operation cycles are used as thetransformation coefficient data F₁ of operation values contained in theequation (45), data −a₆P₆+a₄P₄−a₇P₂−a₅P₀ output from the register 40 ₄in the second operation cycle are used as the transformation coefficientdata F₃ of operation values contained in the equation (45), data−a₅P₆+a₇P₄+a₄P₂+a₆P₀ output from the register 40 ₄ in the thirdoperation cycle are used as the transformation coefficient data F₅ ofoperation values contained in the equation (45) and data−a₇P₆+a₆P₄−a₅P₂+a₄P₀ output from the register 40 ₄ in the fourthoperation cycle are used as the transformation coefficient data F₇ ofoperation values contained in the equation (45). The transformationcoefficient data F₁, F₃, F₅ and F₇ are shown on a lower right side ofthe output line of the register 40 ₄.

By completing the above arithmetic operations, the primary 8-8 DCT oneight pieces of data contained in one line constituting the 8×8 datablock is terminated. The same primary 8-8 DCT as described above isperformed on each of lines subsequent to a next line constituting the8×8 data block and thereafter, and the primary 8-8 DCT on all eightlines constituting the 8×8 data block is terminated in the similarmanner. After the completion of the primary 8-8 DCT on the all eightlines, a secondary 8-8 DCT is performed on each string of eight datastrings constituting the 8×8 data block. The transformation coefficientdata obtained by completing the primary 8-8 DCT and secondary 8-8 DCT isused for compression of input 8×8 picture data. Thus, transmission ofcompressed picture element data is made possible by using thetransformation coefficient data obtained by performing the primary 8-8DCT and secondary 8-8 DCT on the 8×8 picture element data within animage to be transmitted for compression of the 8×8 picture element datablock.

Next, operations for the 2-4-8 DCT will be described. Each of eightpieces of picture element data f₀ to f₇ contained in each line ofpicture elements constituting the 8×8 picture element data block outputsequentially from the MUX 12 is stored into each of the registers 14 ₁to 14 ₈ in a manner that each of the picture element data f₀ to f₇corresponds to each of the registers 14 ₁ to 14 ₈.

Data f₀ stored in the register 14 ₁ is fed to the summand input of theadding circuit 18 ₁ and data f₁ supplied to the register 14 ₂ is fed tothe addend input of the adding circuit 18 ₁ and then data f₀+f₁=b₀ areoutput from the adding circuit 18 ₁. Data f₂ stored in the register 14 ₃is fed to the summand input of the adding circuit 18 ₂ and data f₃supplied to the register 14 ₄ is fed to the addend input of the addingcircuit 18 ₂ and then data f₂+f₃=b₁ are output from the adding circuit18 ₂. Data f₄ stored in the register 14 ₅ is fed to the summand input ofthe adding circuit 18 ₃ and data f₅ stored in the register 14 ₆ is fedto the addend input of the adding circuit 18 ₃ and then data f₄+f₅=b₂are output from the adding circuit 18 ₂. Data f₆ stored in the register14 ₇ is fed to the summand input of the adding circuit 18 ₄ and data f₇stored in the register 14 ₈ is fed to the addend input of the addingcircuit 18 ₄ and then data f₆+f₇=b₃ are output from the adding circuit18 ₄. Data f₀ stored in the register 14 ₁ is fed to the minuend input ofthe subtracting circuit 20 ₁ and data f₁ stored in the register 14 ₂ isfed to the subtrahend input of the subtracting circuit 20 ₁ and thendata f₀−f₁=b₄ are output from the subtracting circuit 20 ₁. Data f₂stored in the register 14 ₃ is fed to the minuend input of thesubtracting circuit 20 ₂ and data f₃ stored in the register 14 ₄ is fedto the subtrahend input of the subtracting circuit 20 ₂ and then dataf₂−f₂=b₅ are output from the subtracting circuit 20 ₂. Data f₄ stored inthe register 14 ₅ is fed to the minuend input of the subtracting circuit20 ₃ and data f₅ stored in the register 14 ₆ is fed to the subtrahendinput of the subtracting circuit 20 ₃ and then data f₄−f₄=b₆ are outputfrom the subtracting circuit 20 ₃. Data f₆ stored in the register 14 ₇is fed to the minuend input of the subtracting circuit 20 ₄ and data f₆stored in the register 14 ₇ is fed to the subtrahend input of thesubtracting circuit 20 ₄ and then data f₆−f₇=b₇ are output from thesubtracting circuit 20 ₃.

Data b₀ to data b₃ output from the adding circuit 18 ₁ to adding circuit18 ₄ are input through the register 22 ₁ to register 22 ₄ to the MUX 24₁ to MUX 24 ₄. MUX 24 ₁ selects the register in the order of theregister 22 ₁, 22 ₄, 22 ₁ and 22 ₄ and sequentially outputs four piecesof data b₀, b₃, b₀ and b₃. MUX 24 ₂ selects the register in the order ofthe register 22 ₃, 22 ₃, 22 ₃ and 22 ₃ and sequentially outputs fourpieces of data b₁, b₂, b₁ and b₂. MUX 24 ₃ selects the register in theorder of the register 22 ₁, 22 ₄, 22 ₂ and 22 ₃ and sequentially outputsfour pieces of data b₀, b₃, b₁ and b₂. MUX 24 ₄ selects the register inthe order of the register 22 ₂, 22 ₃, 22 ₁ and 22 ₄ and sequentiallyoutputs four pieces of data b₁, b₂, b₀ and b₃.

The adding/subtracting circuit 26 ₁ performs adding operations on dataoutput in the first order and second order out of four pieces of datab₀, b₃, b₀ and b₃ given in every operation cycle from a first operationcycle to a second operation cycle out of four operation cycles from theMUX 24 ₁ and on data output in the first order and second order out offour pieces of data b₁, b₂, b₁ and b₂ given in every operation cyclefrom a first operation cycle to a second operation cycle out of fouroperation cycles from the MUX 24 ₂ and performs subtracting operation ondata output in the third order and fourth order out of four pieces ofdata b₀, b₃, b₀ and b₃ given in every operation cycle from a firstoperation cycle to a second operation cycle out of four operation cyclesfrom the MUX 24 ₁ and on data output in the third order and fourth orderout of four pieces of data b₁, b₂, b₁ and b₂ given in every operationcycle from a first operation cycle to a second operation cycle out offour operation cycles from the MUX 24 ₂ and, as a result, outputs datab₀+b₁, data b₃+b₂, data b₀−b₁ and data b₃−b₂. That is, data output inthe first order from the MUX 24 ₁ is added to data output in the secondorder from the MUX 24 ₂ and the same adding and subtracting operationsare performed on other data.

Each of the data b₀+b₁, data b₃+b₂, data b₀−b₁ and data b₃−b₂ outputsequentially from the adding/subtracting circuit 26 ₁, after beingstored in the register 30 ₁ (see the register 30 ₁), is multiplied by afixed coefficient P₃ in the P₃ coefficient multiplying circuit 32 ₁ andstored in order into the register 34 ₁ (see the register 34 ₁ in FIG.5).

Each of data b₀, b₃, b₁ and b₂ output sequentially from the MUX 24 ₃,after being stored in order into the register 30 ₂ (see the register 30₂), is multiplied by a fixed coefficient P₅ in the P₅ coefficientmultiplying circuit 32 ₂ and stored in order into the register 34 ₂ (seethe register 34 ₂). Each of data b₁, b₂, b₀ and b₃ output sequentiallyfrom the MUX 24 ₄, after being stored in order into the register 30 ₃(see the register 30 ₃), is multiplied by a fixed coefficient P₁ in theP₁ coefficient multiplying circuit 32 ₃ and stored in order into theregister 34 ₃ (see the register 34 ₃).

The MUX 24 ₅ selects the register in the order of the register 22 ₅,register 22 ₈, register 22 ₅, register 22 ₈ and sequentially outputsfour pieces of data b₄, b₇, b₄ and b₇. The MUX 24 ₇ selects the registerin the order of the register 22 ₆, register 22 ₇, register 22 ₆,register 24 ₇ and sequentially outputs four pieces of data b₅, b₆, b₅and b₆.

The adding/subtracting circuit 26 ₂ performs adding operations on dataoutput in the first order and second order out of four pieces of datab₄, b₇, b₄ and b₇ given from the MUX 24 ₅ and on data output in thefirst order and second order out of four pieces of data b₅, b₆, b₅ andb₆ given from the MUX 24 ₇ and performs subtracting operations on dataoutput in the first order and second order out of four pieces of datab₄, b₇, b₄ and b₇ given from the MUX 24 ₅ and on data output in thefirst order and second order out of four pieces of data b₅, b₆, b₅ andb₆ given from the MUX 24 ₇ and, as a result, outputs data b₄+b₅, datab₇+b₆, data b₄−b₅ and data b₇−b₆. The data b₄+b₅, data b₇+b₆, data b₄−b₅and data b₇−b₆ output in order are stored through the MUX 28 ₁sequentially into the register 30 ₄ (see the register 30 ₄).

The MUX 24 ₆ selects the register in the order of the registers 22 ₅, 22₈, 22 ₆ and 22 ₇ and sequentially outputs four pieces of data b₄, b₇,b₅and b₆. The four pieces of data b₄, b₇, b₅ and b₆ sequentially outputare stored into the register 30 ₅ (see the register 30 ₅). The MUX 28 ₂selects a “0” four times and sequentially outputs the “0” data. Fourpieces of the “0” data output sequentially are stored in the register 30₆ in order (see the register 30 ₆ in FIG. 6). The MUX 24 ₈ selects theregister in the order of the registers 22 ₆, 22 ₇, 22 ₅ and 22 ₈ andsequentially outputs four pieces of data b₅, b₆, b₄ and b₇. The fourpieces of data b₅, b₆, b₄ and b₇ output in order are stored into theregister 30 ₇ (see the register 30 ₇).

Of data (b₀+b₁) P₃, data (b₃+b₂) P₃, data (b₀−b₁) P₃ and data (b₃−b₂) P₃output sequentially from the register 34 ₁, data (b₀+b₁) P₃ is storedinto the register 40 ₁ in a first operation cycle out of the fouroperation cycles performed by the register 40 ₁ and the AND circuit 36₁, data (b₀+b₁) P₃+(b₃+b₂) P₃ are stored into the register 40 ₁ in thesecond operation cycle, data (b₀+b₁) P₃ is stored into the register 40 ₁in the third operation cycle and data (b₀−b₁) P₃+(b₃−b₂) P₃ are storedinto the register 40 ₁ in the fourth operation cycle (see the register40 ₁ in FIG. 5).

Of data stored in the register 40 ₁ and output therefrom, the data(b₀+b₁) P₃ stored in the register 40 ₁ in the first operation cycle andthe data (b₀−b₁) P₃ stored into the register 40 ₁ in the third operationcycle are undefined values and are not used, as transformationcoefficient data, in the discrete cosine transformation method. Theabove data are indicated with asterisks (*) on a lower left side of theoutput line of the register 40 ₁ in FIG. 2.

The data (b₀+b₁) P₃+(b₃+b₂) P₃ stored in the second operation cycle andthe data (b₀−b₁) P₃+(b₃−b₂) P₃ stored in the fourth operation cycle areused as the transformation coefficient data F₀ and F₂ of operationvalues contained in the equation (51). The transformation coefficientdata F₀ and F₂ are shown on the lower left side of the output line ofthe register 40 ₁.

Of data b₀P₅, data b₃P₅, data b₁P₅, data b₂P₅ output sequentially fromthe register 34 ₂, data b₁P₁, data b₂P₁, data b₀P₁ and b₃P₁ outputsequentially from the register 34 ₃, data b₀P₅, +b₁P₁ is stored into theregister 40 ₂in a first operation cycle out of the four operation cyclesperformed by the adding circuit 38 ₂, the register 40 ₂ and the ANDcircuit 36 ₂, data b₀P₅+b₁P₁−b₃P₅−b₂P₁ is stored into the register 40 ₂in a second operation cycle, data −b₁P₅+b₀P₁ is stored into the register40 ₂ in a third operation cycle, data −b₁P₅+b₀P₁+b₂P₅−b₃P₁ are stored inthe fourth operation cycle (see the register 40 ₂).

Of data stored into the register 40 ₂ and output therefrom, the datab₀P₅, +b₁P₁ and data −b₁P₅+b₀P₁ stored in the first operation and thirdoperation are undefined values and are not used, as transformationcoefficient data, in the discrete cosine transformation method. Theabove data are indicated with asterisks (*) on a lower left side of theoutput line of the register 40 ₂ in FIG. 2.

The data b₀P₅+b₁P₁−b₃P₅−b₂P₁ stored in the second operation cycle andthe data −b₁P₅+b₀P₁+b₂P₅−b₃P₁ stored in the fourth operation cycle areused as the transformation coefficient data F₁ and F₃ of operationvalues contained in the equation (45). The transformation coefficientdata F₁ and F₃ are shown on the lower right side of the output line ofthe register 40 ₁ in FIG. 2.

Each of data b₄+b₅, data b₇+b₆, data b₄−b₅ and data b₇−b₆ storedsequentially into the register 30 ₄ and output sequentially therefrom ismultiplied by the fixed coefficient P₃ in the P₆/P₃ coefficientmultiplying circuit 32 ₄. In the first operation cycle out of the fouroperation cycles, data (b₄+b₅) P₃ output from the P₆/P₃ coefficientmultiplying circuit 32 ₄ and stored in the register 34 ₄ (see theregister 34 ₄ in FIG. 6) is added to “0” data output from the ANDcircuit 36 ₃ and stored into the register 40 ₃ (see the register 40 ₃ inFIG. 6). The data fed to the register 40 ₃ in the first operation cycleis not used as a transformation coefficient data in the 2-4-8 DCT. Theabove data are indicated with asterisks (*) on the lower side of theoutput line of the register 40 ₃ in FIG. 2.

Data (b₄+b₅) P₃ input through the AND circuit 36 ₃ in a second operationcycle out of the four operation cycles and data (b₇+b₆) P₃ output fromthe register 34 ₄ in a second operation cycle out of the four operationcycles are fed to the adding circuit 38 ₃ and data (b₄+b₅) P₃+(b₇+b₆) P₃are output from the adding circuit 38 ₃ and stored into the register 40₃ (see the register 40 ₃). Data fed to the register 40 ₃ in the secondoperation cycle is used as transformation coefficient data F₄ in the2-4-8 DCT. The transformation coefficient data F₄ is shown on the lowerside of the output line of the register 40 ₃ in FIG. 2.

Data (b₄−b₅) P₃ and “0” data are fed to the adding circuit 38 ₃ in athird operation cycle out of the four operation cycles and data (b₄−b₅)P₃ is output from the adding circuit 38 ₃ and stored into the register40 ₃ (see the register 40 ₃ in FIG. 6). The data fed to the register 40₃ in the third operation cycle is not used as the transformationcoefficient data in the 2-4-8 DCT. The above data are indicated withasterisks (*) on a lower side of the output line of the register 40 ₃ inFIG. 2. Data (b₄−b₅) P₃ input through the AND circuit 36 ₃ in the fourthoperation cycle in the four operation cycles and data (b₇−b6) P₃ outputfrom the register 34 ₄ in the fourth operation cycle are fed to theadding circuit 38 ₃ and then data (b₄−b₅) P₃+(b₇−br) P3 is output fromthe adding circuit 38 ₃ and stored in the register 40 ₃ (see theregister 40 ₃). Data fed to the register 40 ₃ in the fourth operationcycle is used as transformation coefficient data F₆ in the 2-4-8 DCT.The transformation coefficient data F₆ is shown in the lower side of theoutput line of the register 40 ₃ in FIG. 2.

Each of data b₄, b₇, b₅ and b₆ stored into the register 30 ₅ in everycycle from a first operation cycle to fourth operation cycle out of fouroperation cycles and output sequentially is multiplied by the fixedcoefficient P₅ in the P₄/P₅ coefficient multiplying circuit 32 ₅. Eachof four pieces of “0” data (see the register 30 ₆) stored in everyoperation cycle from a first operation cycle to fourth operation cycleout of the four operation cycles and output sequentially is multipliedby the fixed coefficient P₅ in the P₄/P₅ coefficient multiplying circuit32 ₅. Each of four pieces of data b₅, b₆, b₄ and b₇ stored into theregister 30 ₇ in every operation cycle from a first operation cycle tofourth operation cycle out of the four operation cycles and outputsequentially is multiplied by the fixed coefficient P₁ in the P₀/P₁coefficient multiplying circuit 32 ₇.

In the 2-4-8 DCT, since the “0” is fed to other input of the AND circuit36 ₄ in every operation cycle from a first operation cycle to fourthoperation cycle out of the four operation cycles and therefore dataoutput from the P₆/P₃ coefficient multiplying circuit 32 ₄ is not fed tothe adding circuit 38 ₄, data b₄P₅, b₇P₅, b₅P₅ and b₆P₅ (see theregister 34 ₅ in FIG. 6) output sequentially from the P₄/P₅ coefficientmultiplying circuit 32 ₅ and stored in order into the register 34 ₅ anddata b₅P₁, b₆P₁, b₄P₁ and b₇P₁ (see the register 34 ₇ in FIG. 6) outputfrom the P₀/P₁ coefficient multiplying circuit 32 ₇ and stored in orderinto the register 34 ₇ are fed to the adding circuit 38 ₄ in everyoperation cycle.

Data b₄P₅+b₅P₁ is output from the adding circuit 38 ₄ and stored intothe register 40 ₄ (see the register 40 ₄ in FIG. 6) in a first operationcycle out of the four operation cycles.

Data fed to the register 40 ₄ in the first operation cycle is not usedas transformation coefficient data in the 2-4-8 DCT. The transformationcoefficient data is shown in a lower left side of the output line of theregister 40 ₄ in FIG. 2.

Data b₄P₅+b₅P₁ input through the AND circuit 36 ₅ in a second operationcycle out of four operation cycles and data −b₇P₅ output from theregister 34 ₅ in the second operation cycle and data −b₆P₁ output fromthe register 34 ₇ in the second operation cycle and data are fed to theadding circuit 38 ₄, and data b₄P₅+b₅P₁−b₇P₅−b₆P₁ is output from theadding circuit 38 ₄ and stored into the register 40 ₄ (see the register40 ₄). Data fed to the register 40 ₄ in the second operation cycle isused as transformation coefficient data F₅ in the 2-4-8 DCT. Thetransformation coefficient data is shown in the lower left side of theoutput line of the register 40 ₄ in FIG. 2.

In a third operation cycle out of the four operation cycles, data−b₅P₅+b₄P₁ is output from the adding circuit 38 ₄ and stored into theregister 40 ₄ (see the register 40 ₄). Data fed to the register 40 ₄ inthe third operation cycle is used as transformation coefficient data inthe 2-4-8 DCT. The above data are indicated with asterisks (*) on thelower left side of the output line of the register 40 ₃ in FIG. 2.

Data −b₅P₅+b₄P₁ input through the AND circuit 36 ₅ in a fourth operationcycle out of the four operation cycles and data b₆P₅ output from theregister 34 ₅ in the fourth operation cycle and −b₇P₁ output from theregister 34 ₇ in the fourth operation cycle are fed to the addingcircuit 38 ₄, and then data −b₅P₅+b₄P₁+b₆P₅−b₇P₁ is output from theadding circuit 38 ₄ and stored into the register 40 ₄ (see the register40 ₄ in FIG. 6). The data fed to the register 40 ₄ in the fourthoperation cycle is used as transformation coefficient data F₇ in the2-4-8 DCT. The DCT coefficient F₇ is shown in the lower left side of theoutput line of the register 40 ₄ in FIG. 2.

By completing the above arithmetic operations, the primary 2-4-8 DCT oneight pieces of data contained in one line constituting the 8×8 datablock is terminated. The same primary 2-4-8 DCT as described above isperformed on each of lines subsequent to a next line constituting the8×8 data block and thereafter, and the primary 2-4-8 DCT on all eightlines constituting the 8×8 data block is terminated in the similarmanner. After the completion of the primary 2-4-8 DCT on the all eightlines, a secondary 2-4-8 DCT is performed on each string of eight datastrings constituting the 8×8 data block and the secondary 2-4-8 DCT isterminated. The transformation coefficient data obtained by completingthe secondary 2-4-8 DCT is used for compression of the input 8×8 pictureelement data. By performing the primary 2-4-8 DCT and secondary 2-4-8DCT on each of the 8×8 picture element data in an image data to betransmitted, the image data is compressed and can be transmitted. Thus,according to the present invention, since the 8-8 DCT device and 2-4-8DCT device are so configured that a part of the fixed coefficientmultiplying circuit used in the 8-8 DCT circuit can be used, by beingswitched, as a fixed coefficient multiplying circuit required in the2-4-8 DCT, a high-speed calculating characteristic obtained through apipeline processing type arithmetic operation in the 8-8 DCT can bemaintained in the 2-4-8 DCT and the high-speed calculatingcharacteristic can be still maintained in even miniaturized 8-8 DCT and2-4-8 DCT devices.

Second Embodiment

FIG. 7 is a schematic block diagram partially showing configurations ofan 8-8/2-4-8 IDCT device according to a second embodiment of the presentinvention. FIG. 8 is also a schematic block diagram partially showingconfigurations of the 8-8/2-4-8 IDCT device according to the secondembodiment. FIG. 9 is a part of a timing chart explaining operations ofan 8-8 IDCT constituting the 8-8/2-4-8 IDCT device according to thesecond embodiment. FIG. 10 is a remaining part of the timing chartexplaining operations of the 8-8 IDCT constituting the 8-8/2-4-8 IDCTaccording to the second embodiment. FIG. 11 is a part of a timing chartexplaining operations of an 2-4-8 IDCT constituting the 8-8/2-4-8 IDCTaccording to the second embodiment. FIG. 12 is a remaining part of thetiming chart explaining operations of the 2-4-8 IDCT constituting the8-8/2-4-8 IDCT according to the second embodiment. By overlaying a lineII—II in FIG. 7 on a line II—II in FIG. 8, an overall configuration ofthe 8-8 DCT/2-4-8 IDCT device can be shown.

Thus, according to the embodiment, since the 8-8 IDCT/2-4-8 IDCT deviceare so configured that a part of the fixed coefficient multiplyingcircuit used in the 8-8 IDCT circuit can be used, by being switched, asa fixed coefficient multiplying circuit required in the 2-4-8 IDCT, ahigh-speed calculating characteristic obtained through a pipelineprocessing type arithmetic operation in the 8-8 IDCT can be maintainedin the 2-4-8 IDCT and the high-speed calculating characteristic can bestill maintained in even miniaturized 8-8 IDCT devices and 2-4-8 IDCTdevices.

Prior to description of configurations of the 8-8 IDCT/2-4-8 IDCTdevice, operational equations used to perform the 8-8 IDCT on every oneline or one string of 8×8 picture element data are first describedbelow.

When f(0), f(1), f(2), f(3), f(4), f(5), f(6) f(7) and F(0, v), F(1, v),F(2, v), F(3, v), F(4, v), F(5, v), F(6, v) and F(7, v) obtained byexpressing two-dimensional equation (18) described in the above“Description of the Related Art” in a form of one-dimensional equation(52) and by decompressing the equation (52) with respect to h and x, asin case of the equation (40), are set so that f(0)=f₀, f(1)=f₁, f(2)=f₂,f(3)=f₃, f(4)=f₄, f(5)=f₅, f(6)=f₆, f(7)=f₇ and F(0, v)=F₀, F(1, v)=F₁,F(2, v)=F₂, F(3, v)=F₃, F(4, v)=F₄, F(5, v)=F₅, F(6, v)=F₆ and F(7,v)=F₇, and the resulting equation is changed and rearranged to obtainequation (53). P₀ to P₆ in the equation (53) are the same values as inthe equation (40). $\begin{matrix}{{{f(x)} = {\sum\limits_{h = 0}^{7}{{C(h)}{F\left( {h,v} \right)}\cos \quad \beta}}}{{\text{where}\quad \beta} \equiv \frac{\pi \quad {h\left( {{2x} + 1} \right)}}{16}}} & (52) \\{\begin{bmatrix}f_{0} \\f_{1} \\f_{2} \\f_{3} \\f_{4} \\f_{5} \\f_{6} \\f_{7}\end{bmatrix} = {\begin{bmatrix}P_{3} & P_{6} & P_{5} & P_{4} & P_{3} & P_{2} & P_{1} & P_{0} \\P_{3} & P_{4} & P_{1} & {- P_{0}} & {- P_{3}} & {- P_{6}} & {- P_{5}} & {- P_{2}} \\P_{3} & P_{2} & {- P_{1}} & {- P_{6}} & {- P_{3}} & P_{0} & P_{5} & P_{4} \\P_{3} & P_{0} & {- P_{5}} & {- P_{2}} & P_{3} & P_{4} & {- P_{1}} & {- P_{6}} \\P_{3} & {- P_{0}} & {- P_{5}} & P_{2} & P_{3} & {- P_{4}} & {- P_{1}} & P_{6} \\P_{3} & {- P_{2}} & {- P_{1}} & P_{6} & {- P_{3}} & {- P_{0}} & P_{5} & {- P_{4}} \\p_{3} & {- P_{4}} & P_{1} & P_{0} & {- P_{3}} & P_{6} & {- P_{5}} & P_{2} \\P_{3} & {- P_{6}} & P_{5} & {- P_{4}} & P_{3} & {- P_{2}} & P_{1} & {- P_{0}}\end{bmatrix}\begin{bmatrix}F_{0} \\F_{1} \\F_{2} \\F_{3} \\F_{4} \\F_{5} \\F_{6} \\F_{7}\end{bmatrix}}} & (53)\end{matrix}$

An equation (54) is obtained by changing a right side of the aboveequation (53) and an equation (55) is obtained by rearranging a rightside of the equation (54). $\begin{matrix}{{\frac{1}{2}\begin{bmatrix}{f_{0} + f_{4}} \\{f_{1} + f_{5}} \\{f_{2} + f_{6}} \\{f_{3} + f_{7}} \\{f_{0} - f_{4}} \\{f_{1} - f_{5}} \\{f_{2} - f_{6}} \\{f_{3} - f_{7}}\end{bmatrix}} = {\begin{bmatrix}P_{3} & 0 & P_{5} & 0 & P_{3} & 0 & P_{1} & 0 \\P_{3} & 0 & P_{1} & 0 & {- P_{3}} & 0 & {- P_{5}} & 0 \\P_{3} & 0 & {- P_{1}} & 0 & {- P_{3}} & 0 & {- P_{5}} & 0 \\P_{3} & 0 & {- P_{5}} & 0 & P_{3} & 0 & {- P_{1}} & 0 \\0 & P_{6} & 0 & P_{4} & 0 & P_{2} & 0 & P_{0} \\0 & P_{4} & 0 & {- P_{0}} & 0 & {- P_{6}} & 0 & {- P_{2}} \\0 & P_{2} & 0 & {- P_{6}} & 0 & P_{0} & 0 & P_{4} \\0 & P_{0} & 0 & {- P_{2}} & 0 & P_{4} & 0 & {- P_{6}}\end{bmatrix}\begin{bmatrix}F_{0} \\F_{1} \\F_{2} \\F_{3} \\F_{4} \\F_{5} \\F_{6} \\F_{7}\end{bmatrix}}} & (54) \\\left. \begin{matrix}{{\frac{1}{2}\begin{bmatrix}{f_{0} + f_{4}} \\{f_{1} + f_{5}} \\{f_{2} + f_{6}} \\{f_{3} + f_{7}}\end{bmatrix}} = {\begin{bmatrix}P_{3} & P_{5} & P_{3} & P_{1} \\P_{3} & P_{1} & {- P_{3}} & {- P_{5}} \\P_{3} & {- P_{1}} & {- P_{3}} & P_{5} \\P_{3} & {- P_{5}} & P_{3} & {- P_{1}}\end{bmatrix}\begin{bmatrix}F_{0} \\F_{2} \\F_{4} \\F_{6}\end{bmatrix}}} \\{{\frac{1}{2}\begin{bmatrix}{f_{0} - f_{4}} \\{f_{1} - f_{5}} \\{f_{2} - f_{6}} \\{f_{3} - f_{7}}\end{bmatrix}} = {\begin{bmatrix}P_{6} & P_{4} & P_{2} & P_{6} \\P_{4} & {- P_{0}} & {- P_{6}} & P_{2} \\P_{2} & {- P_{6}} & P_{0} & P_{4} \\P_{0} & {- P_{2}} & P_{4} & {- P_{6}}\end{bmatrix}\begin{bmatrix}F_{1} \\F_{3} \\F_{5} \\F_{7}\end{bmatrix}}}\end{matrix} \right\} & (55)\end{matrix}$

By further rearranging a right side of the equation (55), an equation(56) is obtained. By setting F₀, F₁, F₂, F₃, F₄, F₅, F₆ and F₇ in theequation (56) to those in equation (57), an equation (58) is obtained.$\begin{matrix}\left. \begin{matrix}{{\frac{1}{2}\begin{bmatrix}{f_{0} + f_{4}} \\{f_{1} + f_{5}} \\{f_{2} + f_{6}} \\{f_{3} + f_{7}}\end{bmatrix}} = {\begin{bmatrix}\left( {F_{0} + F_{4}} \right) & F_{2} & F_{6} \\\left( {F_{0} - F_{4}} \right) & {- F_{6}} & F_{2} \\\left( {F_{0} - F_{4}} \right) & F_{6} & {- F_{2}} \\\left( {F_{0} + F_{4}} \right) & {- F_{2}} & {- F_{6}}\end{bmatrix}\begin{bmatrix}P_{3} \\P_{5} \\P_{1}\end{bmatrix}}} \\{{\frac{1}{2}\begin{bmatrix}{f_{0} - f_{4}} \\{f_{1} - f_{5}} \\{f_{2} - f_{6}} \\{f_{3} - f_{7}}\end{bmatrix}} = {\begin{bmatrix}F_{1} & F_{3} & {- F_{5}} & {- F_{7}} \\F_{5} & F_{1} & F_{7} & {- F_{3}} \\{- F_{3}} & {- F_{7}} & F_{1} & {- F_{5}} \\F_{7} & {- F_{5}} & {- F_{3}} & F_{1}\end{bmatrix}\begin{bmatrix}P_{6} \\P_{4} \\P_{2} \\P_{0}\end{bmatrix}}}\end{matrix} \right\} & (56) \\\left. \begin{matrix}{{c_{0} = F_{0}},\quad {c_{1} = F_{6}},\quad {c_{2} = F_{2}},\quad {c_{3} = F_{4}},} \\{{c_{4} = {- F_{7}}},\quad {c_{5} = F_{1}},\quad {c_{6} = F_{5}},\quad {c_{7} = F_{3}}}\end{matrix} \right\} & (57) \\\left. \begin{matrix}{{\frac{1}{2}\begin{bmatrix}{f_{0} + f_{4}} \\{f_{1} + f_{5}} \\{f_{2} + f_{6}} \\{f_{3} + f_{7}}\end{bmatrix}} = {\begin{bmatrix}{c_{0} + c_{3}} & c_{2} & c_{1} \\{c_{0} - c_{3}} & {- c_{1}} & c_{2} \\{c_{0} - c_{3}} & c_{1} & {- c_{2}} \\{c_{0} + c_{3}} & {- c_{2}} & {- c_{1}}\end{bmatrix}\begin{bmatrix}P_{3} \\P_{5} \\P_{1}\end{bmatrix}}} \\{{\frac{1}{2}\begin{bmatrix}{f_{0} - f_{4}} \\{f_{1} - f_{5}} \\{f_{2} - f_{6}} \\{f_{3} - f_{7}}\end{bmatrix}} = {\begin{bmatrix}c_{5} & c_{7} & {- c_{6}} & {- c_{4}} \\c_{6} & c_{5} & c_{4} & {- c_{7}} \\{- c_{7}} & {- c_{4}} & c_{5} & {- c_{6}} \\c_{4} & {- c_{6}} & c_{7} & c_{5}\end{bmatrix}\begin{bmatrix}P_{6} \\P_{4} \\P_{2} \\P_{0}\end{bmatrix}}}\end{matrix} \right\} & (58)\end{matrix}$

The 8-8 IDCT device constituting the 8-8 IDCT /2-4-8 IDCT device 110according to the second embodiment is operated in accordance with theequation (58).

Next, operational equations used to perform the 2-4-8 IDCT on every oneline or one string constituting 8×8 picture element data are firstdescribed below.

When f(0), f(1), f(2), f(3), f(4), f(5), f(6) f(7) and f(0, z), f(1, z),f(2, z), f(3, z), f(4, z), f(5, z), f(6, z) and f(7, z) obtained byexpressing the two-dimensional equation (18) described in the above“Description of the Related Art” in the form of one-dimensional equation(52) and by decompressing the equation (52) with respect to h and x, asin the case of the equation (40), are set so that f(0)=f₀, f(1)=f₁,f(2)=f₂, f(3)=f₃, f(4)=f₄, f(5)=f₅, f(6)=f₆, f(7)=f₇ and F(0, v)=F₀,F(1, v)=F₁, F(2, v)=F₂, F(3, v)=F₃, F(4, v)=F₄, F(5, v)=F₅, F(6, v)=F₆and F(7, v)=F₇, and the resulting equation is changed and rearranged,equation (60) is obtained. P₀ to P₆ in the equation (60) are the samevalues as in the equation (40). $\begin{matrix}{\left. \begin{matrix}{{f(x)} = {\sum\limits_{h = 0}^{7}{\left\{ {{{C(h)}{F\left( {h,v} \right)}} + {F\left( {h,{v + 4}} \right)}} \right\} \cos \quad \beta}}} \\{{f(x)} = {\sum\limits_{h = 0}^{7}{\left\{ {{{C(h)}{F\left( {h,v} \right)}} - {F\left( {h,{v + 4}} \right)}} \right\} \cos \quad \beta}}}\end{matrix} \right\} {{\text{where}\quad \beta} \equiv \frac{\pi \quad {h\left( {{2x} + 1} \right)}}{16}}} & (59) \\{\begin{bmatrix}f_{0} \\f_{1} \\f_{2} \\f_{3} \\f_{4} \\f_{5} \\f_{6} \\f_{7}\end{bmatrix} = {\begin{bmatrix}P_{3} & P_{5} & P_{3} & P_{1} & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & P_{3} & P_{5} & P_{3} & P_{1} \\P_{3} & P_{1} & {- P_{3}} & {- P_{5}} & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & P_{3} & P_{1} & {- P_{3}} & {- P_{5}} \\P_{3} & {- P_{1}} & {- P_{3}} & P_{5} & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & P_{3} & {- P_{1}} & {- P_{3}} & P_{5} \\P_{3} & {- P_{5}} & P_{3} & {- P_{1}} & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & P_{3} & {- P_{5}} & P_{3} & {- P_{1}}\end{bmatrix}\begin{bmatrix}{F_{0} + F_{4}} \\{F_{1} + F_{5}} \\{F_{2} + F_{6}} \\{F_{3} + F_{7}} \\{F_{0} - F_{4}} \\{F_{1} - F_{5}} \\{F_{2} - F_{6}} \\{F_{3} - F_{7}}\end{bmatrix}}} & (60)\end{matrix}$

An equation (61) is obtained by changing a right side of the aboveequation (60) and an equation (62) is obtained by rearranging a rightside of the equation (61). $\begin{matrix}{\begin{bmatrix}f_{0} \\f_{2} \\f_{4} \\f_{6} \\f_{1} \\f_{3} \\f_{5} \\f_{7}\end{bmatrix} = {\begin{bmatrix}P_{3} & P_{5} & P_{3} & P_{1} & 0 & 0 & 0 & 0 \\P_{3} & P_{1} & {- P_{3}} & {- P_{5}} & 0 & 0 & 0 & 0 \\P_{3} & {- P_{1}} & {- P_{3}} & P_{5} & 0 & 0 & 0 & 0 \\P_{3} & {- P_{5}} & P_{3} & {- P_{1}} & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & P_{3} & P_{5} & P_{3} & P_{1} \\0 & 0 & 0 & 0 & P_{3} & P_{1} & {- P_{3}} & {- P_{5}} \\0 & 0 & 0 & 0 & P_{3} & {- P_{1}} & {- P_{3}} & P_{5} \\0 & 0 & 0 & 0 & P_{3} & {- P_{5}} & P_{3} & {- P_{1}}\end{bmatrix}\begin{bmatrix}{F_{0} + F_{4}} \\{F_{1} + F_{5}} \\{F_{2} + F_{6}} \\{F_{3} + F_{7}} \\{F_{0} - F_{4}} \\{F_{1} - F_{5}} \\{F_{2} - F_{6}} \\{F_{3} - F_{7}}\end{bmatrix}}} & (61) \\\left. \begin{matrix}{\begin{bmatrix}f_{0} \\f_{2} \\f_{4} \\f_{6}\end{bmatrix} = {\begin{bmatrix}{\left( {F_{0} + F_{4}} \right) + \left( {F_{2} + F_{6}} \right)} & \left( {F_{1} - F_{5}} \right) & \left( {F_{3} - F_{7}} \right) \\{\left( {F_{0} + F_{4}} \right) - \left( {F_{2} + F_{6}} \right)} & {- \left( {F_{3} - F_{7}} \right)} & \left( {F_{1} - F_{5}} \right) \\{\left( {F_{0} + F_{4}} \right) - \left( {F_{2} + F_{6}} \right)} & \left( {F_{3} - F_{7}} \right) & {- \left( {F_{1} - F_{5}} \right)} \\{\left( {F_{0} + F_{4}} \right) + \left( {F_{2} + F_{6}} \right)} & {- \left( {F_{1} - F_{5}} \right)} & {- \left( {F_{3} - F_{7}} \right)}\end{bmatrix}\begin{bmatrix}P_{3} \\P_{5} \\P_{1}\end{bmatrix}}} \\{\begin{bmatrix}f_{1} \\f_{3} \\f_{5} \\f_{7}\end{bmatrix} = {\begin{bmatrix}{\left( {F_{0} + F_{4}} \right) + \left( {F_{2} + F_{6}} \right)} & \left( {F_{1} - F_{5}} \right) & \left( {F_{3} - F_{7}} \right) \\{\left( {F_{0} - F_{4}} \right) - \left( {F_{2} + F_{6}} \right)} & {- \left( {F_{3} - F_{7}} \right)} & \left( {F_{1} - F_{5}} \right) \\{\left( {F_{0} - F_{4}} \right) - \left( {F_{2} + F_{6}} \right)} & \left( {F_{3} - F_{7}} \right) & {- \left( {F_{1} - F_{5}} \right)} \\{\left( {F_{0} + F_{4}} \right) + \left( {F_{2} + F_{6}} \right)} & {- \left( {F_{1} - F_{5}} \right)} & {- \left( {F_{3} - F_{7}} \right)}\end{bmatrix}\begin{bmatrix}P_{3} \\P_{5} \\P_{1}\end{bmatrix}}}\end{matrix} \right\} & (62)\end{matrix}$

By setting F₀+F₄, F₃+F₇, F₁+F₅, F₂+F₆, F₀−F₄, F₃−F₇, F₁−F₅, and F₂−F₆ inthe equation (62) in the same manner as those in equation (63), anequation (64) is obtained. The 2-4-8 IDCT device constituting the 8-8IDCT/2-4-8 IDCT device 110 according to the second embodiment isoperated in accordance with the equation (64). $\begin{matrix}\left. \begin{matrix}{{d_{0} = {F_{0} + F_{4}}},\quad {d_{1} = {F_{3} + F_{7}}},\quad {d_{2} = {F_{1} + F_{5}}},\quad {d_{3} = {F_{2} + F_{6}}},} \\{{d_{4} = {F_{0} - F_{4}}},\quad {d_{5} = {F_{3} - F_{7}}},\quad {d_{6} = {F_{1} - F_{5}}},\quad {d_{7} = {F_{2} - F_{6}}}}\end{matrix} \right\} & (63) \\\left. \begin{matrix}{\begin{bmatrix}f_{0} \\f_{2} \\f_{4} \\f_{6}\end{bmatrix} = {\begin{bmatrix}{d_{0} + d_{3}} & d_{2} & d_{1} \\{d_{0} - d_{3}} & {- d_{1}} & d_{2} \\{d_{0} - d_{3}} & d_{1} & {- d_{2}} \\{d_{0} + d_{3}} & {- d_{2}} & {- d_{1}}\end{bmatrix}\begin{bmatrix}P_{3} \\P_{5} \\P_{1}\end{bmatrix}}} \\{\begin{bmatrix}f_{1} \\f_{3} \\f_{5} \\f_{7}\end{bmatrix} = {\begin{bmatrix}{d_{4} + d_{7}} & d_{6} & d_{5} \\{d_{4} - d_{7}} & {- d_{5}} & d_{6} \\{d_{4} - d_{7}} & d_{5} & {- d_{6}} \\{d_{4} + d_{7}} & {- d_{6}} & {- d_{5}}\end{bmatrix}\begin{bmatrix}P_{3} \\P_{5} \\P_{1}\end{bmatrix}}}\end{matrix} \right\} & (64)\end{matrix}$

An MUX 112, in the case of the 8-8 IDCT, selectively outputs each ofeight pieces of data to be used for a primary IDCT out of 8×8transformation coefficient data (hereafter called as “8×8 data”) towhich the 8-8 IDCT is performed or each of eight pieces of datacontained in each line constituting the 8-8 data obtained by the primaryIDCT to each of corresponding registers 14 ₁ to 14 ₈ and, in the case ofthe 2-4-8 IDCT, selectively outputs data F₀ out of the eight pieces ofdata F₀ to F₇ to the register 14 ₁ constituting a first register group113, data F₁ to the register 14 ₅, data F₂ to the register 14 ₃, data F₃to the register 14 ₇, data F₄ to the register 14 ₂, data F₅ to theregister 14 ₆, data F₆ to the register 14 ₄ and data F₇ to the register14 ₈.

MUXs 16 ₁₂, 16 ₂, 16 ₃₂, 16 ₄, 16 ₅, 16 ₆, 16 ₇, 16 ₈ constituting afirst MUX group 15, in the case of the 8-8 IDCT, select “0” data and MUX16 ₁₁ and MUX 16 ₃₁, in the case of the 8-8 IDCT, select a register 14 ₂and a register 14 ₄ respectively. The MUX 16 ₂, 16 ₄ to 16 ₈, in the2-4-8 IDCT, select corresponding registers 14 ₂ and 14 ₄ to 14 ₈,respectively. The MUX 16 ₁₁, 16 ₁₂, 16 ₃₁ and 16 ₃₂, in the case of the2-4-8 IDCT, select the registers 14 ₁, 14 ₂, 14 ₃ and 14 ₄,respectively. A MUX 12 ₄, constituting a second MUX group 12 ₃ isconnected to an output of each of the registers 22 ₁, 22 ₂, 22 ₃ and 22₄ and, in both the 8-8 IDCT and 2-4-8 IDCT, selects the register 22 ₁four times and outputs four pieces of data sequentially. An MUX 12 ₄₂ isconnected to the output of each of the register 22 ₁, 22 ₂, 22 ₃ and 22₄ and, in the case of the 8-8 IDCT, selects the register 22 ₃ four timesand outputs four pieces of data sequentially and, in the case of the2-4-8 IDCT , selects the register 22 ₂ four times and outputs fourpieces of data sequentially. An MUX 12 ₄₃ is connected to the output ofeach of the registers 22 ₁, 22 ₂, 22 ₃ and 22 ₄ and, in the case of 8-8IDCT, selects the register in the order of the registers 22 ₂, 22 ₄, 22₄ and 22 ₂ and outputs four pieces of data in order and, in the case ofthe 2-4-8 IDCT, selects the register in the order of the registers 22 ₃,22 ₄, 22 ₄ and 22 ₃ and outputs four pieces of data sequentially. An MUX12 ₄₄ is connected to the output of each of the registers 22 ₁, 22 ₂, 22₃ and 22 ₄ and, in the case of the 8-8 IDCT, selects the register in theorder of the registers 22 ₄, 22 ₂, 22 ₂ and 22 ₄ and outputs four piecesof data sequentially and, in the case of the 2-4-8 IDCT, selects theregister in the order of the registers 22 ₄, 22 ₃, 22 ₃ and 22 ₄ andoutputs four pieces of data in order. An MUX 12 ₄₅ is connected to theoutput of each of registers 22 ₅, 22 ₆, 22 ₇ and 22 ₈ and, in the caseof the 8-8 IDCT, selects the register in the order of the registers 22₅, 22 ₇, 22 ₆ and 22 ₈ and outputs four pieces of data in order and, inthe case of the 2-4-8 IDCT, selects the register 22 ₃ four times andoutputs four pieces of data sequentially. An MUX 124 ₆ is connected tothe output of each of the registers 22 ₅, 22 ₆, 22 ₇ and 22 ₈ and, inthe 8-8 IDCT, selects the register in the order of the registers 22 ₆,22 ₅, 22 ₈ and 22 ₇ and outputs four pieces of data sequentially and, inthe case of the 2-4-8 IDCT, selects the register in the order of theregisters 22 ₇, 22 ₈, 22 ₈ and 22 ₇ and outputs four pieces of data inorder. An MUX 124 ₇ is connected to the output of each of the registers22 ₅, 22 ₆, 22 ₇ and 22 ₈ and, in the case of the 8-8 IDCT, selects theregister in the order of the registers 22 ₇, 22 ₈, 22 ₅ and 22 ₆ andoutputs four pieces of data and, in the case of the 2-4-8 IDCT, selectsthe register 22 ₆ four times and outputs four pieces of data in order.An MUX 124 ₈ is connected to the output of each of the registers 22 ₅,22 ₆, 22 ₇ and 22 ₈ and, in the case of the 8-8 IDCT, selects theregister in the order of the registers 22 ₈, 22 ₆, 22 ₇ and 22 ₆₅ andoutputs four pieces of data sequentially and, in the case of the 2-4-8IDCT, selects the register 22 ₈, 22 ₇, 22 ₇ and 22 ₈ and outputs fourpieces of data sequentially.

An adding/subtracting circuit 126 ₁ constituting a firstadding/subtracting circuit group 125 performs adding operations on dataout of four pieces of data output sequentially from the MUX 124 ₁ and ondata out of four pieces of data output sequentially from the MUX 124 ₂in a first order and fourth order, and performs subtracting operationson data output in a second order and third order out of four pieces ofdata output from the MUX 124 ₁ and from the MUX 124 ₂; that is, dataoutput in the first order from the MUX 124 ₁ is added to data output inthe first order from the MUX 124 ₂ and thus same adding operations areperformed on data output in the fourth order, and the similarsubtracting operations are performed on data output in the second orderand third order. In the subtracting operation performed by theadding/subtracting circuit 126 ₁, data output from the MUX 124 ₂ issubtracted from data output from the MUX 124 ₁.

An adding/subtracting circuit 126 ₂ constituting the firstadding/subtracting circuit group 125 performs adding operations on dataout of four pieces of data output sequentially from the MUX 124 ₅ and ondata out of four pieces of data output sequentially from the MUX 124 ₇in a first order and fourth order, and performs subtracting operationson data output in a second order and third order out of four pieces ofdata output from the MUX 124 ₅ and from the MUX 124 ₇; that is, dataoutput in the first order from the MUX 124 ₁ is added to data output inthe first order from the MUX 124 ₇ and thus same adding operations areperformed on data output in the fourth order, and the similarsubtracting operations are performed on data output in the second orderand third order. In the subtracting operation performed by theadding/subtracting circuit 126 ₂, data output from the MUX 124 ₇ issubtracted from data output from the MUX 124 ₅.

A register 134 ₁ constituting a fourth register group 133, in both the8-8 IDCT and 2-4-8 IDCT, stores each of four pieces of data outputsequentially from a P₅ coefficient multiplying circuit 32 ₂ and outputseach of all the data as positive values. A register 134 ₂ constitutingthe fourth register group 133, in both the 8-8 IDCT and 2-4-8 IDCT,stores each of four pieces of data output sequentially from a P₅coefficient multiplying circuit 32 ₂ and outputs data stored in a firstorder and third order as positive values and data stored in a secondorder and fourth order as negative values. A register 134 ₃, in both the8-8 IDCT and the 2-4-8 IDCT, stores each of four pieces of data outputsequentially from a P₁ coefficient multiplying circuit 32 ₃ and outputsdata stored in the first order and second order as positive values anddata stored in the third order and fourth order as negative values.

A register 134 ₄ stores each of four pieces of data output sequentiallyfrom a P₆/P₃ coefficient multiplying circuit 32 ₄ and, in the case ofthe 8-8 IDCT, outputs data to be output in a first order, second orderand fourth order as positive values and data to be output in a thirdorder as negative values and, in the case of the 2-4-8 IDCT, outputseach of all the data stored as positive values. A register 134 ₅ storeseach of four pieces of data output sequentially from a P₄/P₅ and, in thecase of the 8-8 IDCT, outputs data to be output in a first order andsecond order as positive values and data output in a third order andfourth order as negative values and, in the case of the 2-4-8 IDCT,outputs data in the first order and third order as positive values anddata to be output in the second and fourth order as negative values. Aregister 134 ₆ stores each of four pieces of data output sequentiallyfrom a P₂ coefficient multiplying circuit 32 ₆ and outputs data to beoutput in a first order and fourth order as negative values and data tobe output in the second order and third order as positive orders. Aregister 134 ₇ stores each of four pieces of data output sequentiallyfrom a P₀/P₁ coefficient multiplying circuit 32 ₇ and, in the case ofthe 8-8 IDCT, outputs data to be output in a first order to third orderas negative values and data output in a fourth order as a positive valueand, in the case of the 2-4-8 IDCT, outputs data in the first order andsecond order and data output in a third order and fourth order asnegative values.

An adding circuit 138 ₂ performs adding operations on data stored in theregister 134 ₁, data stored in the register 134 ₂ and data stored in theregister 134 ₃. Data output sequentially from the adding circuit 138 ₂is stored into a register 40 ₂ in order. An adding circuit 138 ₄performs adding operations on data stored in the register 134 ₄, datastored in the register 134 ₅, data stored into a register 134 ₆ and datastored in the register 134 ₇. Data output from the adding circuit 138 ₄is stored in the register 40 ₄.

Data from the register 40 ₂ is fed to a summand input of an addingcircuit 44 and to a minuend input of a subtracting circuit 42 and datafrom the register 40 ₄ is fed to an addend input of the adding circuit44 and to a subtrahend input of the subtracting circuit 42. Data outputfrom the subtracting circuit 42 is fed to a register 46 constituting asixth register group 45 and data from the adding circuit 44 is fed to aregister 48 constituting the sixth register group 45.

Moreover, configurations of the second embodiment are the same as thosein the first embodiment except those described above. Therefore, in FIG.7 and FIG. 8, same numbers are given to components being same as thosein FIG. 1 and FIG. 2 in the first embodiment and descriptions of themare omitted.

However, configurations of the register 134 ₁ are the same as those ofthe register 34 ₁. The adding circuit 18 ₁ is connected to the output ofthe register 14 ₁ and of the MUX 16 ₂, the adding circuit 18 ₂ isconnected to the output of the register 14 ₃ and of the MUX 16 ₄, theadding circuit 18 ₃ is connected to the output of the register 14 ₅ andof the MUX 16 ₄ and the adding circuit 18 ₄ is connected to the outputof the register 14 ₇ and of the MUX 16 ₈. Moreover, the subtractingcircuit 20 ₁ is connected to the output of each of the MUX 16 ₁₁ and MUX16 ₁₂, the subtracting circuit 20 ₂ is connected to the output of theMUX 16 ₃₁ and MUX 16 ₃₂, the subtracting circuit 20 ₃ is connected tothe register 14 ₆ and the MUX 16 ₂₂, the subtracting circuit 20 ₃ isconnected to the output of the register 14 ₆ and of the MUX 16 ₅ and thesubtracting circuit 20 ₄ is connected to the output of the register 14 ₈and of the MUX 16 ₈.

Next, operations in the second embodiment will be described by referringto FIG. 7 to FIG. 12. First, operations in the 8-8 IDCT will beexplained.

Each of eight pieces of data F₀ to F₇ existing in a string direction outof 8×8 image data compressed by the 8-8 DCT is stored into each ofcorresponding register 14 ₁ to register 14 ₈ constituting the firstregister group 113.

Since the MUXs 16 ₁₂, 16 ₂, 16 ₃₂, 16 ₄, 16 ₅, 16 ₆, 16 ₇ and 16 ₈ haveselected the “0” data and the MUX 16₁₁ and MUX 16 ₃₁ have selected theregister 14 ₂ and register 14 ₄ respectively, data F₀=a₀ is output fromthe adding circuit 18 ₁, data F₂=a₂ from the adding circuit 18 ₂, dataF₄=a₃ from the adding circuit 18 ₃ and data F₆=a₁ from the addingcircuit 18 ₄, and data F₁=a₅ is output from the subtracting circuit 20₁, F₃=a₇ from the subtracting circuit 20 ₂, data −F₅=a₆ from thesubtracting circuit 20 ₃ and data −F₇=a₄ from the subtracting circuit 20₄.

Data a₀ to a₃ output sequentially from the adding circuit 18 ₁ to 18 ₄are input to the MUX 12 ₄, to MUX 124 ₄ through the register 22 ₁ toregister 22 ₄. The adding/subtracting circuit 126 performs addingoperations and subtracting operations to data a₀ output sequentially inevery operation cycle from a first cycle to fourth operation cycle outof the four operation cycles from the MUX 124 ₁ and to data a₃ outputsequentially in every operation cycle from a first operation cyclefourth operation cycle out of the four operation cycles from 124 ₂ and,as a result, data a₀+a₃, data a₀−a₃, data a₀−a₃ and data a₀+a₃ areoutput in order.

Data a₀+a₃, data a₀−a₃, data a₀−a₃ and data a₀+a₃ output sequentiallyfrom the adding/subtracting circuit 126 ₁ are stored in the 30 ₁ (seethe register 30 ₁ in FIG. 9). Data a₂, data a₁, data a₁ and data a₂output in every operation cycle from a first operation cycle to fourthoperation cycle out of the four operation cycles from the MUX 124 ₃ anddata a₁, data a₂, data a₂ and data a₁ output in every operation cyclefrom a first operation cycle to fourth operation cycle out of the fouroperation cycles from the MUX 124 ₄ are stored into the register 30 ₃sequentially (see the register 30 ₃ in FIG. 9).

Data a₅, data a₆, data a₇ and data a₄ output in every operation cyclefrom a first operation cycle to fourth operation cycle out of the fouroperation cycles from the MUX 124 ₅ are stored into the register 30 ₄sequentially (see the register 30 ₄ in FIG. 10). Data a₇, data a₅, dataa₄ and data a₆ output in every operation cycle from a first operationcycle to fourth operation cycle out of the four operation cycles fromthe MUX 124 ₆ are stored into the register 30 ₅ sequentially (see theregister 30 ₅ in FIG. 10). Data a₆, data a₄, data a₅ and data a₇ outputin every operation cycle from a first operation cycle to fourthoperation cycle out of the four operation cycles are stored into theregister 30 ₆ (see the register 30 ₆ in FIG. 10). Data a₄, data a₇, dataa₆ and data a₅ output in every operation cycle from a first operationcycle to fourth operation out of the four operation cycles are storedinto the register 30 ₇ sequentially (see the register 30 ₇ in FIG. 10).

Data stored sequentially into the register 30 ₁ is multiplied by a fixedcoefficient P₃ in the P₃ coefficient multiplying circuit 32 ₁ andresulting data is stored in order into the register 13 ₄, (see theregister 13 ₄, in FIG. 9). Data stored sequentially into the register 30₂ is multiplied by a fixed coefficient P₅ in the P₅ coefficientmultiplying circuit 32 ₂ and resulting data is stored in order into theregister 134 ₂ (see the register 134 ₂ in FIG. 9). Data storedsequentially into the register 30 ₃ is multiplied by a fixed coefficientP₁ in the P₁ coefficient multiplying circuit 32 ₃ and resulting data isstored in order into the register 134 ₃ (see the register 134 ₃ in FIG.9). Data stored sequentially into the register 30 ₄ is multiplied by afixed coefficient P₆ in the P₆ coefficient multiplying circuit 32 ₄ andresulting data is stored into the register 134 ₄ sequentially (see theregister 134 ₄ in FIG. 10). Data stored sequentially into the register30 ₅ is multiplied by a fixed coefficient P₄ in the P₄/P₅ coefficientmultiplying circuit 32 ₅ and resulting data is stored in order into theregister 134 ₅ (see the register 34 ₅ in FIG. 10). Data storedsequentially stored in the register 30 ₆ is multiplied by a fixedcoefficient P₂ in the P₂ coefficient multiplying circuit 32 ₆ andresulting data is stored in order into the register 134 ₆ (see theregister 134 ₆ in FIG. 10). Data stored in order into the register 30₇is multiplied by a fixed coefficient P₀ in the P₀/P₁ coefficientmultiplying circuit 32 ₇ and resulting data is stored in order into theregister 134 ₇ (see the register 134 in FIG. 10).

The adding circuit 138 ₂ performs adding operations on each of data fedfrom the register 134 ₁, register 134 ₂ and register 134 ₃ in the orderof a first operation cycle to fourth operation cycle out of the fouroperation cycles and output data (a₀+a₃) P₃+a₂P₅+a₁P₁, (a₀−a₃)P₃−a₁P₅+a₂P₁, (a₀−a₃) P₃+a₁P₅−a₂P₁, (a₀+a₃) P₃−a₂P₅−a₁P₁) are stored inorder into the register 40 ₂ (see the register 40 ₂ in FIG. 9).

The adding circuit 138 ₄ performs adding operations on each of data fedfrom the register 134 ₄, register 134 ₅ and register 134 ₆ in the orderof a first operation cycle to fourth operation cycle out of the fouroperation cycles and output data a₅P₆+a₇P₄−a₆P₂−a₄P₀,a₆P₆+a₅P₄+a₄P₂−a₇P₀, −a₇P₆−a₄P₄+a₅P₂−a₆−P₀, a₄P₆−a₆P₄−a₇P₂+a₅P₀ arestored in order into the register 40 ₄ (see the register 40 ₄ in FIG.9).

When data stored into the register 40 ₂ and output in every secondoperation cycle is multiplied by data being stored in the register 40 ₄and output in every second operation cycle in the adding circuit 44,data f₀ out of data f₀ to data f₇ existing before a compression isperformed on eight pieces of data F₀ to data F₇ arranged in a stringdirection constituting input 8×8 data block is obtained in a firstoperation cycle, data f₁ out of data f₀ to data f₇ existing before thecompression is performed on input eight pieces of data F₀ to data F₇ isobtained in a second operation cycle, data f₂ out of data f₀ to data f₇existing before the compression is performed on input eight pieces ofdata F₀ to data F₇ is obtained in a third operation cycle and data f₃out of data f₀ to data f₇ existing before the compression is performedon input eight pieces of data F₀ to data F₇ is obtained in a fourthoperation cycle. The data f₀, data f₁, data f₂ and data f₃ are storedsequentially into the register 48. In FIG. 8, the image data f₀ to imagedata f₃ to be stored in the register 48, corresponding to eight piecesof data F₀ to data F₇, are shown in a lower part of the output line ofthe register 48.

Moreover, when data being stored in the register 40 ₄ and output in asecond operation cycle is subtracted from data being stored in theregister 40 ₂ and output in a second operation cycle in the subtractingcircuit 42, data f₄ out of data f₀ to data f₇ existing before acompression is performed on eight pieces of data F₀ to data F₇ arrangedin a string direction constituting input 8×8 data block is obtained in afirst operation cycle, data f₅ out of data f₀ to data f₇ existing beforethe compression is performed on input eight pieces of data F₀ to data F₇is obtained in a second operation cycle, data f₆ out of data f₀ to dataf₇ existing before the compression is performed on input eight pieces ofdata F₀ to data F₇ is obtained in a third operation cycle and data f₇out of data f₀ to data f₇ existing before the compression is performedon input eight pieces of data F₀ to data F₇ is obtained in a fourthoperation cycle. Data f₄, data f₅, data f₆ and data f₇ are storedsequentially into the register 46 (see the register 46 in FIG. 10). InFIG. 8, the image data f₄ to image data f₇ to be stored in the register46, corresponding to eight pieces of data F₀ to data F₇, are shown inthe lower part of the output line of the register 48.

By completing the above arithmetic operations, the primary 8-8 IDCT oneight pieces of data contained in one string constituting the 8×8 datablock is terminated. The same primary 8-8 IDCT as described above isperformed on each of strings subsequent to a next string constitutingthe 8×8 data block and thereafter, and the primary 8-8 IDCT on all eightstrings constituting the 8×8 data block is terminated in the similarmanner. After the completion of the primary 8-8 IDCT on the all eightstrings, a secondary 8-8 IDCT is performed on eight pieces of data(transposed data for IDCT) contained in each line constituting the 8×8data block. By completing the primary 8-8 IDCT and secondary 8-8 IDCT tobe performed on each of the 8×8 pieces of data, the transmitted imagedata compressed by the 8-8 DCT can be reproduced.

Next, operations in the 2-4-8 IDCT will be described below. Each ofeight pieces of data F₀ to data F₇ out of 8×8 data block obtained byperforming the 2-4-8 DCT, arranged in the string direction in 8×8transformation coefficient data transmitted sequentially from the MUX112 is stored into each of the register 14 ₁ to register 14 ₈constituting the first register group 113 as follows: That is, the dataF₀ is stored into the register 14 ₁, data F₄ into the register 14 ₂,data F₂ into the register 14 ₃, data F₆ into the register 14 ₄, data F₁into the register 14 ₅, data F₅ into the register 14 ₆, data F₃ into theregister 14 ₇ and data F₇ into the register 14 ₈.

Since the MUX 16 ₂, MUX 16 ₄ to MUX 16 ₈ have selected the correspondingregister 14 ₁, register 14 ₄ to register 14 ₈ and the MUX 16 ₁₁, MUX 16₁₂, MUX 16 ₃₁, MUX 16 ₃₂ have selected the corresponding register 14 ₁,register 14 ₃, register 14 ₃, register 14 ₄, data F₀+F₄=b₀ is outputfrom the adding circuit 18 ₁, data F₂+F₆=b₃ from the adding circuit 18₂, data F₁+F₅=b₂ from the adding circuit 18 ₃, data F₃+F₇=b₁ from theadding circuit 18 ₄, data F₀−F₄=b₄ from the subtracting circuit 20 ₁,data F₂−F₆=b₇ from the subtracting circuit 20 ₂ and data F₃−F₇=b₅ fromthe subtracting circuit 20 ₄.

Data b₀ to data b₃ output from the adding circuit 18 ₁ to adding circuit18 ₄ are input to the MUX 124 ₁ to MUX 124 ₄ through the register 22 ₁to register 22 ₄. Adding operations and subtracting operations areperformed, by the adding and subtracting circuits 126 ₁, sequentially ondata b₀ output from the MUX 124 ₁ in every operation cycle from a firstoperation cycle to fourth operation cycle out of the four operationcycles and on data b₃ output from the MUX 124 ₂ in every operation cyclefrom a first operation cycle to fourth operation cycle out of the fouroperation cycles and, as a result, data b₀+b₃, data b₀−b₃, data b₀−b₃and data b₀+b₃ are output in order. Data b₀+b₃, data b₀−b₃, datab_(0 - b) ₃ and b₀+b₃ output sequentially from the adding/subtracting126 ₁ are stored in the register 30 ₁ (see the register 30 ₁ in FIG.11).

Data b₂, data b₁, data b₁ and data b₂ output from the MUX 124 ₃ in everyoperation cycle from a first operation cycle to fourth operation cycleout of the four operation cycles are stored in order into the register30 ₂ (see the register 30 ₂ in FIG. 11) and data b₁, data b₂, data b₂and data b₁ output from the MUX 124 ₄ in every operation cycle from afirst operation to fourth operation cycle out of the four operationcycles are stored in order into the register 30 ₃ (see the register 30 ₃in FIG. 11).

Adding operations and subtracting operations are performed by theadding/subtracting circuit 126 ₂ on data b₄, data b₄, data b₄ and datab₄ output from the MUX 124 ₅ in every operation cycle from a firstoperation cycle to fourth operation cycle out of the four operationcycles and on data b₇, data b₇, data b₇ and data b₇ output from the MUX124 ₇ in every operation cycle from a first operation cycle to fourthoperation cycle out of the four operation cycles, and data b₄+b₇, datab₄−b₇, data b₄−b₇ and data b₄+b₇ are output from the adding/subtractingcircuit 126 ₂. Data b₄+b₇, data b₄−b₇, data b₄−b₇ and data b₄+b₇ arestored sequentially into the register 30 ₄ (see the register 30 ₄ inFIG. 11).

Data b₆, data b₅, data b₅ and data b₆ output from the MUX 124 ₆ in everyoperation cycle from a first operation cycle to fourth operation cycleout of the four operation cycles are stored sequentially into theregister 30 ₅ (see the register 30₅ in FIG. 11). Data b₇, data b₇, b₇and b₇ output from the MUX 124 ₇ in every operation cycle from a firstoperation to fourth operation out of the four operation cycles are allnot selected by the MUX 28 ₂ and four pieces of “0” data selected by theMUX 28 ₂ are stored sequentially into the register 30 ₆ (see theregister 30 ₆ in FIG. 11). Data b₅, data b₆, data b₆ and data b₅ outputfrom the MUX 124 ₈ in every operation cycle from a first operation tofourth operation out of the four operation cycles are storedsequentially into the register 30 ₇ (see the register 30 ₇ in FIG. 11).

Each of data sequentially stored into the register 30 ₁ is multiplied bya fixed coefficient P₃ in the P₃ coefficient multiplying circuit 32 ₁and the resulting data are stored in order into the register 13 ₄ (seethe register 134 ₁ in FIG. 11). Each of data sequentially stored intothe register 30 ₂ is multiplied by a fixed coefficient P₅ in the P₅coefficient multiplying circuit 32 ₂ and the resulting data are storedin order into the register 134 ₂ (see the register 134 ₂ in FIG. 11).Each of data stored in order into the register 30 ₃ is multiplied by afixed coefficient P₁ in the P₁ coefficient multiplying circuit 32 ₁ andthe resulting data are stored in order into the register 134 ₃ (see theregister 134 ₃ in FIG. 11). Each of data stored in order in the register30 ₄ is multiplied by a fixed coefficient P₃ in the P₆/P₃ coefficientmultiplying circuit 32 ₄ and the resulting data are stored sequentiallyinto the register 134 ₄ (see the register 134 ₄ in FIG. 12). Each ofdata stored in order into the register 30 ₅ is multiplied by a fixedcoefficient P₅ in the P₄/P₅ coefficient multiplying circuit 32 ₅ and theresulting data are stored sequentially into the register 134 ₅ (see theregister 134 ₅ in FIG. 12). Each of data stored in order into theregister 30 ₆ is multiplied by a fixed coefficient P₂ in the P₂coefficient multiplying circuit 32 ₆ and the resulting data are storedsequentially into the register 134 ₆ (see the register 134 ₆ in FIG.12). Each of data stored in order into the register 30 ₇ is multipliedby a fixed coefficient P₁ in the P₀/P₁ coefficient multiplying circuit32 ₇ and the resulting data is stored sequentially into the register 134₇ (see the register 134 ₇ in FIG. 12).

Data output from the registers 134 ₁, 134 ₂ and 134 ₃ in every operationcycle from a first operation to fourth operation out of four operationcycles are added in the adding circuit 138 ₂, and data (b₀+b₃)P₃+b₂P₅+b₁P₁ as data obtained in the first operation cycle is outputfrom the adding circuit 138 ₂, (b₀−b₃) P₃−b₁P₅+b₂P₁ as data obtained inthe second operation cycle is output, data (b₀−b₃) P₃+b₁P₅−b₂P₁ as dataobtained in the third operation cycle is output and data (b₀+b₃)P₃−b₂P₅−b₁P₁ as data obtained in the fourth operation cycle is outputand the data are stored sequentially into the register 40 ₂. Data to bestored sequentially into the register 40 ₂ include data f₀, data f₂,data f₄ and data f₆ (corresponding to f₀, f₂, f₄ and f₆ in the equation(64)), in the order of storing, out of picture element data f₀ topicture element data f₇ corresponding to input eight pieces of data F₀to data F₇. In FIG. 8, the picture element data f₀, picture element dataf₂, picture element data f₄ and picture element data f₆ are shown in alower part of an output line of the register 40 ₂.

Data output from the register 134 ₄, register 134 ₅ and register 134 ₆in every operation cycle from a first operation to fourth operation outof four operation cycles are added in the adding circuit 138 ₄, and data(b₄+b₇) P₃+b₆P₅+b₅P₁ as data obtained in the first operation cycle isoutput from the adding circuit 138 ₄, (b₄−b₇) P₃−b₅P₅+b₆P₁ as dataobtained in the second operation cycle is output, data (b₄−b₇)P₃+b₅P₅−b₆P₁ as data obtained in the third operation cycle is output anddata (b₄+b₇) P₃−b₆P₅−b₅P₁ as data obtained in the fourth operation cycleis output and the data are stored sequentially into the register 40 ₄.Data to be stored sequentially into the register 40 ₄ include data f₁,data f₃, data f₅ and data f₇ (corresponding to f₁, f₃, f₅ and f₇ in theequation (64)), in the order of storing, out of picture element data f₀to picture element data f₇ corresponding to input eight pieces of dataF₀ to data F₇. In FIG. 8, the picture element data f₁, picture elementdata f₃, picture element data f₅ and picture element data f₇ are shownin a lower part of an output line of the register 40 ₄.

By completing the above arithmetic operations, the primary 2-4-8 IDCT oneight pieces of data contained in one string constituting the 8×8 datablock is terminated. The same primary 2-4-8 IDCT as described above isperformed on each of strings subsequent to a next string constitutingthe 8×8 data block and thereafter, and the primary 2-4-8 IDCT on alleight strings constituting the 8×8 data block is terminated in thesimilar manner. After the completion of the primary 2-4-8 IDCT on alleight strings, a secondary 2-4-8 IDCT is performed on eight data(transposed data for IDCT) contained in each line constituting the 8×8data block. By completing the primary 2-4-8 IDCT and secondary 2-4-8IDCT to be performed on each of the 8×8 data, the transmitted image datacompressed by the 2-4-8 DCT can be reproduced.

Thus, according to the present invention, since the 8-8 IDCT device and2-4-8 IDCT device are so configured that a part of the fixed coefficientmultiplying circuit used in the 8-8 IDCT circuit can be used, by beingswitched, as a fixed coefficient multiplying circuit required in the2-4-8 IDCT, a high-speed calculating characteristic obtained through apipeline-processing type arithmetic operation in the 8-8 IDCT can bemaintained in the 2-4-8 IDCT and the high-speed calculatingcharacteristic can be still maintained in even miniaturized 8-8 IDCTdevices and 2-4-8 IDCT devices.

Third Embodiment

FIG. 13 is a schematic block diagram partially showing electricalconfigurations of a 16-16/2-8-16 DCT device according to a thirdembodiment of the present invention. FIG. 14 is a schematic blockdiagram partially showing electrical configurations of the 16-16/2-8-16DCT device according to the third embodiment. By overlaying a lineIII—III in FIG. 13 on a line III—III in FIG. 14, overall configurationsof the 16-16/2-8-16 DCT device can be shown. Configurations of the16-16/2-8-16 DCT of the third embodiment differ greatly from those inthe first embodiment and second embodiment in that the 16-16 DCT or2-8-16 DCT is performed on 16×16 pieces of picture element data to beinput. The 16-16 DCT/2-8-16 DCT device 210, in the case of the 16-16DCT, performs arithmetic operations according to a determinant equation(65) obtained by decompressing and rearranging the equation (17) and, inthe case of the 2-8-16 DCT, performs arithmetic operations according toa determinant equation (66) obtained by decompressing and rearrangingthe equation (21). Value e₀ to value e₁₅ in the determinant equation(66) are given by the equation (67) and values g₀ to value g₁₅ in thedeterminant equation (66) are given by the equation (68).$\begin{matrix}\left. \begin{matrix}{\begin{bmatrix}F_{0} \\F_{8} \\F_{2} \\F_{6} \\F_{10} \\F_{14} \\F_{4} \\F_{12}\end{bmatrix} = {\begin{bmatrix}{e_{0} + e_{1} + e_{2} + e_{3} +} & \quad & \quad & \quad & \quad & \quad & \quad \\{e_{4} + e_{5} + e_{6} + e_{7}} & 0 & 0 & 0 & 0 & 0 & 0 \\{e_{0} - e_{1} - e_{2} + e_{3} +} & \quad & \quad & \quad & \quad & \quad & \quad \\{e_{4} - e_{5} - e_{6} + e_{7}} & 0 & 0 & 0 & 0 & 0 & 0 \\0 & {e_{0} - e_{3} -} & {e_{1} - e_{2} -} & \quad & \quad & \quad & \quad \\\quad & {e_{4} + e_{7}} & {e_{5} + e_{6}} & 0 & 0 & 0 & 0 \\0 & {{- e_{1}} + e_{2} -} & {e_{0} - e_{2} -} & \quad & \quad & \quad & \quad \\\quad & {e_{5} - e_{6}} & {e_{4} + e_{7}} & 0 & 0 & 0 & 0 \\0 & 0 & 0 & {e_{0} - e_{7}} & {e_{1} - e_{6}} & {e_{2} - e_{5}} & {e_{3} - e_{4}} \\0 & 0 & 0 & {e_{5} - e_{2}} & {e_{0} - e_{6}} & {e_{3} - e_{4}} & {e_{6} - e_{1}} \\0 & 0 & 0 & {e_{6} - e_{1}} & {e_{3} - e_{4}} & {e_{0} - e_{7}} & {e_{2} - e_{5}} \\0 & 0 & 0 & {e_{4} - e_{3}} & {e_{2} - e_{5}} & {e_{6} - e_{1}} & {e_{0} - e_{7}}\end{bmatrix}\begin{bmatrix}P_{7} \\P_{11} \\P_{3} \\P_{13} \\P_{9} \\P_{5} \\P_{1}\end{bmatrix}}} \\{\begin{bmatrix}F_{1} \\F_{3} \\F_{5} \\F_{7} \\F_{9} \\F_{11} \\F_{13} \\F_{15}\end{bmatrix} = {\begin{bmatrix}e_{8} & e_{9} & e_{10} & e_{11} & e_{12} & e_{13} & e_{14} & e_{15} \\{- e_{13}} & e_{8} & {- e_{12}} & {- e_{14}} & e_{9} & {- e_{11}} & {- e_{15}} & e_{10} \\e_{14} & {- e_{11}} & e_{8} & {- e_{10}} & e_{13} & e_{15} & {- e_{12}} & e_{9} \\e_{12} & {- e_{10}} & {- e_{14}} & e_{8} & {- e_{15}} & {- e_{9}} & e_{13} & e_{11} \\e_{11} & {- e_{13}} & {- e_{9}} & e_{15} & e_{8} & e_{14} & {- e_{10}} & {- e_{12}} \\{- e_{9}} & {- e_{12}} & {- e_{15}} & e_{13} & e_{10} & e_{8} & e_{11} & e_{14} \\e_{10} & e_{15} & {- e_{11}} & {- e_{9}} & {- e_{14}} & e_{12} & e_{8} & e_{13} \\{- e_{15}} & e_{14} & {- e_{13}} & {- e_{12}} & {- e_{11}} & e_{10} & {- e_{9}} & e_{8}\end{bmatrix}\begin{bmatrix}P_{14} \\P_{12} \\P_{10} \\P_{8} \\P_{6} \\P_{4} \\P_{2} \\P_{0}\end{bmatrix}}}\end{matrix} \right\} & (65) \\\left. \begin{matrix}{\begin{bmatrix}F_{0} \\F_{4} \\F_{2} \\F_{6} \\F_{3} \\F_{5} \\F_{1} \\F_{7}\end{bmatrix} = {\begin{bmatrix}{g_{0} + g_{1} + g_{2} + g_{3} +} & 0 & 0 & 0 & 0 & 0 & 0 \\{g_{4} + g_{5} + g_{6} + g_{7}} & \quad & \quad & \quad & \quad & \quad & \quad \\{g_{0} - g_{1} - g_{2} + g_{3} +} & 0 & 0 & 0 & 0 & 0 & 0 \\{g_{4} - g_{5} - g_{6} + g_{7}} & \quad & \quad & \quad & \quad & \quad & \quad \\0 & {g_{0} + g_{7} -} & {g_{1} - g_{2} -} & 0 & 0 & 0 & 0 \\\quad & {g_{3} - g_{4}} & {g_{5} + g_{6}} & \quad & \quad & \quad & \quad \\0 & {{- g_{1}} + g_{2} +} & {g_{0} - g_{3} -} & 0 & 0 & 0 & 0 \\\quad & {g_{5} - g_{6}} & {g_{4} - g_{7}} & \quad & \quad & \quad & \quad \\0 & 0 & 0 & {{- g_{2}} + g_{5}} & {g_{0} - g_{7}} & {{- g_{3}} + g_{4}} & {{- g_{1}} + g_{6}} \\0 & 0 & 0 & {{- g_{1}} + g_{6}} & {g_{3} - g_{4}} & {g_{0} - g_{7}} & {g_{2} - g_{5}} \\0 & 0 & 0 & {g_{0} - g_{7}} & {g_{1} - g_{6}} & {g_{2} - g_{5}} & {g_{3} - g_{4}} \\0 & 0 & 0 & {{- g_{3}} + g_{4}} & {g_{2} - g_{5}} & {{- g_{2}} + g_{6}} & {g_{0} - g_{7}}\end{bmatrix}\begin{bmatrix}P_{7} \\P_{11} \\P_{3} \\P_{13} \\P_{9} \\P_{5} \\P_{1}\end{bmatrix}}} \\{\begin{bmatrix}F_{8} \\F_{12} \\F_{10} \\F_{14} \\F_{9} \\F_{11} \\F_{13} \\F_{15}\end{bmatrix} = {\begin{bmatrix}{g_{8} + g_{9} + g_{10} + g_{11} +} & 0 & 0 & 0 & 0 & 0 & 0 \\{g_{12} + g_{13} + g_{14} + g_{15}} & \quad & \quad & \quad & \quad & \quad & \quad \\{g_{8} - g_{9} - g_{10} + g_{11} +} & 0 & 0 & 0 & 0 & 0 & 0 \\{g_{12} - g_{13} - g_{14} + g_{15}} & \quad & \quad & \quad & \quad & \quad & \quad \\0 & {g_{8} - g_{11} -} & {g_{9} - g_{10} -} & 0 & 0 & 0 & 0 \\\quad & {g_{12} + g_{15}} & {g_{13} + g_{14}} & \quad & \quad & \quad & \quad \\0 & {{- g_{9}} + g_{10} +} & {g_{8} + g_{11} +} & 0 & 0 & 0 & 0 \\\quad & {g_{13} - g_{14}} & {g_{12} + g_{15}} & \quad & \quad & \quad & \quad \\0 & 0 & 0 & {g_{8} - g_{15}} & {g_{9} - g_{14}} & {g_{10} - g_{13}} & {g_{11} - g_{12}} \\0 & 0 & 0 & {{- g_{10}} + g_{13}} & {g_{8} - g_{15}} & {{- g_{11}} + g_{12}} & {{- g_{9}} + g_{14}} \\0 & 0 & 0 & {{- g_{9}} + g_{14}} & {g_{11} - g_{12}} & {g_{8} - g_{15}} & {g_{10} - g_{13}} \\0 & 0 & 0 & {{- g_{11}} + g_{12}} & {g_{10} - g_{13}} & {{- g_{9}} + g_{14}} & {g_{8} - g_{15}}\end{bmatrix}\begin{bmatrix}P_{7} \\P_{11} \\P_{3} \\P_{13} \\P_{9} \\P_{5} \\P_{1}\end{bmatrix}}}\end{matrix} \right\} & (66) \\\left. \begin{matrix}{{e_{0} = {f_{0} + f_{15}}},\quad {e_{1} = {f_{1} + f_{14}}},\quad {e_{2} = {f_{2} + f_{13}}},\ldots \quad,{e_{7} = {f_{7} + f_{8}}},} \\{{e_{8} = {f_{0} - f_{15}}},\quad {e_{9} = {f_{1} - f_{14}}},\quad {e_{10} = {f_{2} - f_{13}}},\ldots \quad,{e_{15} = {f_{7} - f_{8}}}}\end{matrix} \right\} & (67) \\\left. \begin{matrix}{{g_{0} = {f_{0} + f_{1}}},\quad {g_{1} = {f_{2} + f_{3}}},\quad {g_{2} = {f_{4} + f_{5}}},\ldots \quad,{g_{7} = {f_{14} + f_{15}}},} \\{{g_{8} = {f_{0} - f_{1}}},\quad {g_{9} = {f_{2} - f_{3}}},\quad {g_{10} = {f_{4} - f_{5}}},\ldots \quad,{g_{15} = {f_{14} - f_{15}}}}\end{matrix} \right\} & (68)\end{matrix}$

The values P₀ to P₁₅ in the equation (65) and equation (66) are asfollows:

P₀=cos(15π/32)=−cos(17π/32)=0.09801714034 . . .

P₁=cos(14π/32)=−cos(18π/32)=0.195090322 . . .

P₂=cos(13π/32)=−cos(19π/32)=0.2902846773 . . .

P₃=cos(12π/32)=−cos(20π/32)=0.3826834324 . . .

P₄=cos(11π/32)=−cos(21π/32)=0.4713967368 . . .

P₅=cos(10π/32)=−cos(22π/32)=0.555570233 . . .

P₆=cos(9π/32)=−cos(23π/32)=0.634393842 . . .

P₇=cos(8π/32)=−cos(24π/32)=0.707106781 . . .

P₈=cos(7π/32)=−cos(25π/32)=0.7730104534 . . .

P₉=cos(6π/32)=−cos(26π/32)=0.8314696123 . . .

P₁₀=cos(5π/32)=−cos(27π/32)=0.8819212644 . . .

P₁₁=cos(4π/32)=−cos(28π/32)=0.9238795325 . . .

P₁₂=cos(3π/32)=−cos(29π/32)=0.9567403357 . . .

P₁₃=cos(2π/32)=−cos(30π/32)=0.9807852804 . . .

P₁₄=cos(π/16)=−cos(31π/32)=0.9951847276 . . .

P₁₅=cos(0π)=−cos(π)=1

The 16-16 DCT/2-8-16 DCT 210 of this embodiment is so constructed that apart of a fixed coefficient multiplying circuit is used in the common byboth the 16-16 DCT and the 2-8-16 DCT to perform a pipeline-typehigh-speed arithmetic operations and that the 16-16 DCT and the 2-8-16DCT can be performed even in the miniaturized circuit.

The 16-16 DCT/2-8-16 DCT device of the third embodiment is composed of aMUX 212, sixteen registers 14 ₁ to register 14 ₁₆ constituting a firstregister group 213, eight adding circuits 18 ₁ to 18 ₈ constituting afirst adding circuit group 217, eight subtracting circuits 20 ₁ tosubtracting circuit 20 ₈ constituting a subtracting circuit group 219,sixteen registers 22 ₁ to register 22 ₁₆ constituting a second registergroup 221, sixteen MUXs 224 ₁ to MUX 224 ₁₆ constituting a first MUXgroup 223, two adding/subtracting circuits, adding/subtracting circuit226 ₁ and adding/subtracting circuit 226 ₂ constituting a firstadding/subtracting circuit group 225, two MUXs, MUX 28 ₁ and MUX 28 ₂constituting a second MUX group 227, fifteen registers 30 ₁ to register30 ₁₅ constituting a third register group 229, a P₇ coefficientmultiplying circuit 232 ₁, a P₁₁ coefficient multiplying circuit 232 ₂,a P₃ coefficient multiplying circuit 232 ₃, a P₁₃ coefficientmultiplying circuit 232 ₄, a P₉ coefficient multiplying circuit 232 ₅, aP₅ coefficient multiplying circuit 232 ₆, a P₁ coefficient multiplyingcircuit 232 ₇, a P₁₄/P₇ coefficient multiplying circuit 232 ₈, a P₁₂/P₁₁coefficient multiplying circuit 232 ₉, a P₁₀/P₃ coefficient multiplyingcircuit 232 ₁₀, a P₈/P₁₃ coefficient multiplying circuit 232 ₁₁, a P₆/P₉coefficient multiplying circuit 232 ₁₂, a P₄/P₅ coefficient multiplyingcircuit 232 ₁₃, a P₂ coefficient multiplying circuit 232₁₄, a P₀/P₁coefficient multiplying circuit 232 ₁₅, fifteen registers 234 ₁ toregister 234 ₁₅ constituting a fourth register group 233, six addingcircuits 238 ₁ to adding circuit 238 ₆ constituting a second addingcircuit group 237, eight AND circuits 236 ₁ to AND circuit 236 ₉ and sixregisters 40 ₁ to register 40 ₆ constituting a fifth register group 39.In FIG. 13, each of register 14 ₁ to register 14 ₆ are shown as R.

The MUX 212 selectively outputs each of sixteen pieces of picture data,to which a primary DCT is performed, which is contained in each lineconstituting a block composed of 16×16 pieces of picture data or each ofsixteen pieces of picture data, obtained from the primary DCT, which iscontained in each string constituting the block composed of the 16×16pieces of picture data. Hereinafter, each of sixteen pieces of dataoutput from the MUX 212 is referred to as data f₀ to data f₁₆. The MUX212, in the case of the 16-16 DCT, stores data f₀ into the register 14 ₁constituting the first register group 213, data f₁₅ into the register 14₂, data f₁ into the register 14 ₃, data f₁₄ into the register 14 ₄, dataf₂ into the register 14 ₅, data f₁₃ into the register 14 ₆, data f₃ intothe register 14 ₇, data f₁₂ into the register 14 ₈, data f₄ into theregister 14 ₉, data f₁₁ into the register 14 ₁₀, data f₅ into theregister 14 ₁₁, data f₁₀ into the register 14 ₁₂, data f₆ into theregister 14 ₁₃, data f₉ into the register 14 ₁₄, data f₇ into theregister 14 ₁₅ and data f₈ into the register 14 ₁₆ and, in the case ofthe 2-4-8 DCT, stores data f₀ to data f₁₅ to corresponding register 14 ₁to register 14 ₁₆.

Each of the adding circuits 18 ₁ to adding circuit 18 ₈ constituting thefirst adding circuit group 217, in both the 16-16 DCT and 2-8-16 DCT,performs adding operations on data stored in two registers. That is, theadding circuit 18 ₁ adds data stored in the register 14 ₁ to data storedin the register 14 ₂. The adding circuit 18 ₂ adds stored in theregister 14 ₃ to data stored in the register 14 ₄. The adding circuit 18₃ adds data stored in the register 14 ₅ to data stored in the register14 ₆. The adding circuit 18 ₄ adds data in the register 14 ₇ to datastored in the register 14 ₈. The adding circuit 18 ₅ adds data stored inthe register 14 ₉ to data stored in the register 14 ₁₀. The addingcircuit 18 ₆ adds data stored in the register 14 ₁₁ to data stored inthe register 14 ₁₂. The adding circuit 18 ₇ adds data stored in theregister 14 ₁₃ to data stored in the register 14 ₁₄. The adding circuit18 ₈ adds data stored in the register 14 ₁₅ to data stored in theregister 14 ₁₆.

Each of the subtracting circuit 20 ₁ to subtracting circuit 20 ₈, in thecase of both the 16-16 DCT and the 2-4-8 DCT, performs subtractingoperations on data stored in two registers. That is, the subtractingcircuit 20 ₁ subtracts data stored in the register 14 ₂ from data storedin the register 14 ₁. The subtracting circuit 20 ₂ subtracts data storedin the register 14 ₄ from data stored in the register 14 ₃. Thesubtracting circuit 20 ₃ subtracts data stored in the register 14 ₆ fromdata stored in the register 14 ₅. The subtracting circuit 20 ₄ subtractsdata stored in the register 14 ₈ from data stored in the register 14 ₇.The subtracting circuit 20 ₅ subtracts data stored in the register 14 ₁₀from data stored in the register 14 ₉. The subtracting circuit 20 ₆subtracts data stored in the register 14 ₁₂ from data stored in theregister 14 ₁₁. The subtracting circuit 20 ₇ subtracts data stored inthe register 14 ₁₄ from data stored in the register 14 ₁₃. Thesubtracting circuit 20 ₈ subtracts data stored in the register 14 ₁₆from data stored in the register 14 ₁₅.

The register 22 ₁ constituting the second register group 221 storestemporarily data output from the adding circuit 18₁. The register 22 ₂stores temporarily data output from the adding circuit 18 ₂. Theregister 22 ₃ stores temporarily data output from the adding circuit 18₃. The register 22 ₄ stores temporarily data output from the addingcircuit 18 ₄. The register 22 ₅ temporarily stores data output from theadding circuit 18 ₅. The register 22 ₆ temporarily stores data outputfrom the adding circuit 18 ₆. The register 22 ₇ temporarily stores dataoutput from the adding circuit 18 ₇. The register 22 ₈ temporarilystores data output from the adding circuit 18 ₈.

The register 22 ₉ temporarily stores data output from the subtractingcircuit 20 ₁. The register 22 ₁₀ temporarily stores data output from thesubtracting circuit 20 ₂. The register 22 ₁₁ temporarily stores dataoutput from the subtracting circuit 20 ₃. The register 22 ₁₂ temporarilystores data output from the subtracting circuit 20 ₄. The register 22 ₁₃temporarily stores data output from the subtracting circuit 20 ₅. Theregister 22 ₁₄ temporarily stores data output from the subtractingcircuit 20 ₆. The register 22 ₁₅ temporarily stores data output from thesubtracting circuit 20 ₇. The register 22 ₁₆ temporarily stores outputfrom the subtracting circuit 20 ₈.

Operations of selecting data in the MUX 224 ₁, to MUX 224 ₄ constitutingthe first MUX group 223, in the case of the 16-16 DCT, are as follows:

The MUX 224 ₁ is connected to each of outputs of the register 22 ₁ toresister 22 ₈ and selects the register in the order of the registers 22₁, 22 ₄, 22 ₅, 22 ₈, 22 ₁, 22 ₄, 22 ₅ and 22 ₈ and outputs sequentiallyeight pieces of data. The MUX 224 ₂ is connected to each of outputs ofthe register 22 ₁ to register 22 ₈ and selects the register in the orderof the registers 22 ₂, 22 ₃, 22 ₆, 22 ₇, 22 ₂, 22 ₃, 22 ₆ and 22 ₇ andoutputs sequentially eight pieces of data. The MUX 224 ₃ is connected toeach of outputs of the register 22 ₁ to register 22 ₈ and selects theregister in the order of the registers 22 ₁, 22 ₄, 22 ₅, 22 ₈, 22 ₂, 22₃, 22 ₆ and 22 ₇and outputs sequentially eight pieces of data. The MUX224 ₄ is connected to each of outputs of the register 22 ₁ to register22 ₈ and selects the register in the order of the registers 22 ₂, 22 ₃,22 ₆, 22 ₇, 22 ₁, 22 ₄, 22 ₅ and 22 ₈ and outputs sequentially eightpieces of data.

Operations for selecting data in the MUX 22 ₄, to MUX 224 ₈ in the caseof the 2-8-16 DCT are as follows:

The MUX 224 ₁ is connected to each of outputs of the register 22 ₁ toregister 22 ₈, selects the register in the order of the registers 22 ₁,22 ₄, 22 ₅, 22 ₈, 22 ₁, 22 ₄ 22 ₅ and 22 ₈ and outputs eight pieces ofdata sequentially. The MUX 224 ₂ is connected to each of the outputs ofthe register 22 ₁ to register 22 ₈, and selects the register in theorder of the registers 22 ₂, 22 ₃, 22 ₅, 22 ₇, 22 ₂, 22 ₂, 22 ₃, 22 ₆and 22 ₇ and outputs eight pieces of data sequentially. The MUX 224 ₃ isconnected to each of the outputs of the register 22 ₁ to register 22 ₈,selects the register in the order of the registers 22 ₁, 22 ₈, 22 ₄, 22₅, 22 ₂, 22 ₃, 22 ₆, and 22 ₇ and outputs eight pieces of datasequentially. The MUX 224 ₄ is connected to each of the outputs of theregister 22 ₁ to register 22 ₈, selects the register in the order of theregisters 22 ₂, 22 ₃, 22 ₆, 22 ₇, 22 ₁, 22 ₄, 22 ₅, and 22 ₈ and outputseight pieces of data sequentially.

Operations for selecting data in the MUX 224 ₅ to MUX 224 ₈, in the caseof the 16-16 DCT, are as follows:

The MUX 224 ₅ is connected to each of outputs of the register 22 ₁ toregister 22 ₈ and selects the register in the order of the registers 22₁, 22 ₈, 22 ₆, 22 ₃, 22 ₇, 22 ₂, 22 ₅ and 22 ₄ and outputs sequentiallyeight pieces of data. The MUX 224 ₆ is connected to each of outputs ofthe register 22 ₁ to register 22 ₈ and selects the register in the orderof the registers 22 ₂, 22 ₇, 22 ₁, 22 ₇, 22 ₄, 22 ₅, 22 ₃ and 22 ₆ andoutputs sequentially eight pieces of data. The MUX 224 ₇ is connected toeach of outputs of the register 22 ₁ to register 22 ₈ and selects theregister in the order of the registers 22 ₃, 22 ₆, 22 ₄, 22 ₅, 22 ₁, 22₈, 22 ₂ and 22 ₂ and outputs sequentially eight pieces of data. The MUX224 ₈ is connected to each of outputs of the register 22 ₁ to register22 ₈ and selects the register in the order of the registers 22 ₄, 22 ₅,22 ₇, 22 ₂, 22 ₃, 22 ₆, 22 ₁ and 22 ₈ and outputs sequentially eightpieces of data.

Operations for selecting data in the MUX 224 ₅ to MUX 224 ₈, in the caseof the 2-8-16 DCT are as follows:

The MUX 224 ₅ is connected to each of outputs of the register 22 ₁ toregister 22 ₈ and selects the register in the order of the registers 22₃, 22 ₆, 22 ₂, 22 ₇, 22 ₁, 22 ₈, 22 ₄ and 22 ₅ and outputs sequentiallyeight pieces of data. The MUX 224 ₆ is connected to each of the outputsof the register 22 ₁ to register 22 ₈ and selects the register in theorder of the registers 22 ₂, 22 ₈, 22 ₄, 22 ₅, 22 ₂, 22 ₇, 22 ₃ and 22 ₆and outputs sequentially eight pieces of data. The MUX 224 ₇ isconnected to each of the outputs of the register 22 ₁ to register 22 ₈and selects the register in the order of the registers 22 ₄, 22 ₅, 22 ₁,22 ₈, 22 ₃, 22 ₆, 22 ₂ and 22 ₇ and outputs sequentially eight pieces ofdata. The MUX 224 ₈ is connected to each of the outputs of the register22 ₁ to register 22 ₈ and selects the register in the order of theregisters 22 ₂, 22 ₇, 22 ₃, 22 ₆, 22 ₄, 22 ₅, 22 ₁ and 22 ₈ and outputssequentially eight pieces of data.

Operations of selecting data in the MUX 224 ₉ to MUX 224 ₁₆ constitutingthe first MUX group 223 are different between the 16-16 DCT and the2-8-16 DCT. First, operations of selecting data in the MUX 22 ₉ to MUX22 ₁₆ for the 16-16 DCT are as follows:

The MUX 224 ₉ is connected to each of outputs of the register 22 ₉ toregister 22 ₁₆ and selects the register in the order of 22 ₉, 22 ₁₄, 22₁₅, 22 ₁₃, 22 ₁₂, 22 ₁₀, 22 ₁₁ and 22 ₁₆ and sequentially outputs eightpieces of data. The MUX 224 ₁₀ is connected to each of the outputs ofthe register 22 ₉ to register 22 ₁₆ and selects the register in theorder of 22 ₁₀, 22 ₉, 22 ₁₂, 22 ₁₁, 22 ₁₄, 22 ₁₃, 22 ₁₆ and 22 ₁₅ andsequentially outputs eight pieces of data. The MUX 224 ₁₁ is connectedto each of the outputs of the register 22 ₉ to register 22 ₁₆ andselects the register in the order of 22 ₁₁, 22 ₁₃, 22 ₉, 22 ₁₅, 22 ₁₀,22 ₁₆, 22 ₁₂ and 22 ₁₄ and sequentially outputs eight pieces of data.The MUX 224 ₁₂ is connected to each of the outputs of the register 22 ₉to register 22 ₁₆ and selects the register in the order of 22 ₁₂, 22 ₁₅,22 ₁₁, 22 ₉, 22 ₁₆, 22 ₁₄, 22 ₁₀ and 22 ₁₃ and outputs eight pieces ofdata. The MUX 224 ₁₃ is connected to each of the outputs of the register22 ₉ to register 22 ₁₆ and selects the register in the order of 22 ₁₃,22 ₁₀, 22 ₁₄, 22 ₁₆, 22 ₉, 22 ₁₁, 22 ₁₅ and 22 ₁₂ and sequentiallyoutputs eight pieces of data. The MUX 224 ₁₄ is connected to each of theoutputs of the register 22 ₉ to register 22 ₁₆ and selects the registerin the order of 22 ₁₄, 22 ₁₂, 22 ₁₆, 22 ₁₀, 22 ₁₅, 22 ₉, 22 ₁₃ and 22 ₁₁and sequentially outputs eight pieces of data. The MUX 224 ₁₅ isconnected to each of the outputs of the register 22 ₉ to register 22 ₁₆and selects the register in the order of 22 ₁₅, 22 ₁₆, 22 ₁₃, 22 ₁₄, 22₁₁, 22 ₁₂, 22 ₉ and 22 ₁₀ and sequentially outputs eight pieces of data.The MUX 224 ₁₆ is connected to each of the outputs of the register 22 ₉to register 22 ₁₆ and selects the register in the order of 22 ₁₆, 22 ₁₁,22 ₁₀, 22 ₁₂, 22 ₁₃, 22 ₁₅, 22 ₁₄ and 22 ₉ and sequentially outputseight pieces of data.

Next, operations of selecting data in the MUX 22 ₉ to MUX 22 ₁₆ for the2-8-16 DCT will be described below.

The MUX 224 ₉ is connected to each of outputs of the register 22 ₉ toregister 22 ₁₆ and selects the register in the order of 22 ₉, 22 ₁₂, 22₁₃, 22 ₁₆, 22 ₉, 22 ₁₂, 22 ₁₃ and 22 ₁₆ and sequentially outputs eightpieces of data. The MUX 224 ₁₀ is connected to each of the outputs ofthe register 22 ₉ to register 22 ₁₆ and selects the register in theorder of 22 ₉, 22 ₁₆, 22 ₁₂, 22 ₁₃, 22 ₁₀, 22 ₁₁, 22 ₁₄ and 22 ₁₅ andsequentially outputs eight pieces of data. The MUX 224 ₁₁ is connectedto each of the outputs of the register 22 ₉ to register 22 ₁₆ andselects the register in the order of 22 ₁₀, 22 ₁₁, 22 ₁₄, 22 ₁₅, 22 ₉,22 ₁₂, 22 ₁₃ and 22 ₁₆ and sequentially outputs eight pieces of data.The MUX 224 ₁₂ is connected to each of the outputs of the register 22 ₉to register 22 ₁₆ and selects the register in the order of 22 ₉, 22 ₁₆,22 ₁₁, 22 ₁₄, 22 ₁₀, 22 ₁₅, 22 ₁₂ and 22 ₁₃ and sequentially outputseight pieces of data. The MUX 224 ₁₃ is connected to each of the outputsof the register 22 ₉ to register 22 ₁₆ and selects the register in theorder of 22 ₁₀, 22 ₁₅, 22 ₉, 22 ₁₆, 22 ₁₂, 22 ₁₃, 22 ₁₁ and 22 ₁₄ andsequentially outputs eight pieces of data. The MUX 224 ₁₄ is connectedto each of the outputs of the register 22 ₉ to register 22 ₁₆ andselects the register in the order of 22 ₁₁, 22 ₁₄, 22 ₁₂, 22 ₁₃, 22 ₉,22 ₁₆, 22 ₁₀ and 22 ₁₅ and sequentially outputs eight pieces of data.The MUX 224 ₁₅ is connected to each of the outputs of the register 22 ₉to register 22 ₁₆ and selects the register in the order of 22 ₁₀, 22 ₁₁,22 ₁₄, 22 ₁₅, 22 ₁₀, 22 ₁₁, 22 ₁₃ and 22 ₁₄ and sequentially outputseight pieces of data. The MUX 224 ₁₆ is connected to each of the outputsof the register 22 ₉ to register 22 ₁₆ and selects the register in theorder of 22 ₁₂, 22 ₁₃, 22 ₁₀, 22 ₁₅, 22 ₁₁, 22 ₁₄, 22 ₉ and 22 ₁₆ andsequentially outputs eight pieces of data.

The adding/subtracting circuit 226 ₁ constituting an adding/subtractingcircuit group 225, in both the 16-16 DCT and 2-4-8 DCT, performs addingoperations on data output in a first order to fourth order out of eightpieces of data output sequentially from the MUX 224 ₁ and out of eightpieces of data output sequentially from the MUX 224 ₂ and performssubtracting operations on data output in a fifth order to eighth orderout of eight pieces of data output sequentially from the MUX 224 ₁ andout of eight pieces of data output sequentially from the MUX 224 ₂. Thatis, the adding/subtracting circuit 226 ₁ subtracts data output from theMUX 224 ₂ from data output from the MUX 224 ₁. The adding/subtractingcircuit 226 ₂, in both the 16-16 DCT and 2-4-8 DCT, performs addingoperations on data output in a first order to fourth order out of eightpieces of data output sequentially from the MUX 224 ₉ and out of eightpieces of data output sequentially from the MUX 224 ₁₅ and performssubtracting operations on data output in a fifth order to eighth orderout of eight pieces of data output sequentially from the MUX 224 ₉ andout of eight pieces of data output sequentially from the MUX 224 ₁₅. Theadding/subtracting circuit 226 ₂ subtracts data output from the MUX 224₁₅ from data output from the MUX 224 ₉.

The MUX 28 ₁ constituting the second MUX group 227, in the case of the16-16 DCT, selects eight pieces of data output sequentially from the MUX224 ₉ and, in the case of the 2-4-8 DCT, selects data outputsequentially from the adding/subtracting circuit 226 ₂.

The MUX 28 ₁ constituting the second MUX group 227, in the case of the16-16 DCT, selects eight pieces of data output sequentially from the MUX224 ₉ and, in the case of the 2-8-16 DCT, selects data outputsequentially from the adding/subtracting circuit 226 ₂. The MUX 28 ₂, inthe case of the 16-16 DCT, selects eight pieces of data outputsequentially from the MUX 224 ₁₅ and, in the 2-4-8 DCT, does not selecteight pieces of data output sequentially from the 224 ₁₅ but selects a“0” eight times which corresponds to the eight operation cycles of theMUX 28 ₂.

The register 30 ₁ constituting the third register group 229 sequentiallystores results of the operations on eight pieces of data output in orderfrom the adding/subtracting circuit 226 ₁. The register 30 ₂sequentially stores eight pieces of data output in order from the MUX224 ₃. The register 30 ₃ sequentially stores eight pieces of dataoutput, in order, from the MUX 224 ₄. The register 30 ₄ sequentiallystores eight pieces of data output in order from the MUX 224 ₅. Theregister 30 ₅ sequentially stores eight pieces of data output, in order,from the MUX 224 ₆. The register 30 ₆ sequentially stores eight piecesof data output in order from the MUX 224 ₇. The register 30 ₇sequentially stores eight pieces of data output in order from the MUX224 ₈.

The register 30 ₈ sequentially stores results of operations on eightpieces of data output, in order, from the MUX 224 ₉. The register 30 ₉sequentially stores eight pieces of data output in order from the MUX224 ₁₀. The register 30 ₁₀ sequentially stores eight pieces of dataoutput, in order, from the MUX 224 ₁₁. The register 30 ₁₁ sequentiallystores eight pieces of data output, in order, from the MUX 224 ₁₂. Theregister 30 ₁₂ sequentially stores eight pieces of data output, inorder, from the MUX 224 ₁₃. The register 30 ₁₃ sequentially stores eightpieces of data output in order from the MUX 224 ₁₄. The register 30 ₁₅sequentially stores eight pieces of data output, in order, from the MUX224 ₁₆.

Each of the P₇ coefficient multiplying circuit 232 ₁ to the P₁coefficient multiplying circuit 232 ₇, in the case of both the 16-16 DCTand 2-8-16 DCT, multiplies data output from each of the registers by asame fixed coefficient. That is, the P₇ coefficient multiplying circuit232 ₁ multiplies each of eight pieces of data output sequentially fromthe register 30 ₁ by a fixed coefficient P₇. The P₁₁ coefficientmultiplying circuit 232 ₂ multiplies each of eight pieces of data outputfrom the register 30 ₂ by a fixed coefficient P₁₁. The P₃ coefficientmultiplying circuit 232 ₃ multiplies each of eight pieces of data outputfrom the register 30 ₃ by a fixed coefficient P₃. The P₁₃ coefficientmultiplying circuit 232 ₄ multiplies each of eight pieces of data outputsequentially from the register 30 ₄ by a fixed coefficient P₁₃. The P₉coefficient multiplying circuit 232 ₅ multiplies each of eight pieces ofdata output sequentially from the register 30 ₅ by a fixed coefficientP₉. The P₅ coefficient multiplying circuit 232 ₆ multiplies each ofeight pieces of data by a fixed coefficient P₅. The P₁ coefficientmultiplying circuit 232 ₇ multiplies each of eight pieces of data outputsequentially from the register 30 ₇ by a fixed coefficient P₁.

Each of the P₁₄/P₇ coefficient multiplying circuits 232 ₈ to the P₄/P₅coefficient multiplying circuit 232 ₁₅, in the case of the both 16-16DCT and the 2-8-16 DCT, is adapted to switch a fixed coefficient andperforms a multiplication using another fixed coefficient. That is, theP₁₄/P₇ coefficient multiplying circuit 232 ₈, in the case of the 16-16DCT, multiplies each of eight pieces of data output sequentially fromthe register 30 ₈ by the fixed coefficient P₁₄ and, in the case of the2-4-16 DCT, multiplies each of eight pieces of data output sequentiallyfrom the register 30 ₈ by the fixed coefficient P₇. The P₁₂/P₁₁coefficient multiplying circuit 232 ₉, in the case of the 16-16 DCT,multiplies each of eight pieces of data output sequentially from theregister 30 ₉ by the fixed coefficient P₁₂ and, in the case of the 2-4-8DCT, multiplies each of eight pieces of data output sequentially fromthe register 30 ₉ by the fixed coefficient P₁₁. The P₁₀/P₃ coefficientmultiplying circuit 232 ₁₀, in the case of the 16-16 DCT, multiplieseach of eight pieces of data output sequentially from the register 30 ₁₀by the fixed coefficient P₁₀ and, in the case of the 2-8-16 DCT,multiplies each of eight pieces of data output sequentially from theregister 30 ₁₀ by the fixed coefficient P₃. The P₈/P₁₃ coefficientmultiplying circuit 232 ₁₁, in the case of the 16-16 DCT, multiplieseach of eight pieces of data output sequentially from the register 30 ₁₁and, in the case of the 2-4-8 DCT, multiplies each of eight pieces ofdata output sequentially from the register 30 ₁₁ by the fixedcoefficient P₁₃. The P₆/P₉ coefficient multiplying circuit 232 ₁₂, inthe case of the 16-16 DCT, multiplies each of eight pieces of dataoutput sequentially from the register 30 ₁₂ by the fixed coefficient P₆and, in the case of the 2-8-16 DCT, multiplies each of eight pieces ofdata output sequentially from the register 30 ₁₂ by the fixedcoefficient P₉. The P₄/P₅ coefficient multiplying circuit 232 ₁₃, in thecase of the 16-16 DCT, multiplies each of eight pieces of data outputsequentially from the register 30 ₁₃ by the fixed coefficient P₄ and, inthe case of the 2-4-8 DCT, multiplies each of eight pieces of dataoutput sequentially from the register 30 ₁₃ by the fixed coefficient P₅.The P₂ coefficient multiplying circuit 232 ₁₄ multiplies each of eightpieces of data output sequentially from the register 30 ₁₄ by the fixedcoefficient P₂. The P₀/P₁ coefficient multiplying circuit 232 ₁₅multiplies each of eight pieces of data output sequentially from theregister 30 ₁₅ by the fixed coefficient P₀ and, in the case of the 2-4-8DCT, multiplies each of eight pieces of data output sequentially fromthe register 30 ₁₅ by the fixed coefficient P₁.

Each of the registers 234 ₁, 234 ₃, 234 ₅ and 234 ₁₄ constituting thefourth register group 233, in the case of both the 16-16 DCT and the2-4-8 DCT, sequentially stores and outputs data as follows:

The register 234 ₁ sequentially stores each of eight pieces of dataoutput in order from the P₇ coefficient multiplying circuit 232 ₁ andsequentially outputs each of the data as a positive value. The register234 ₃ sequentially stores each of eight pieces of data outputsequentially from the P₃ coefficient multiplying circuit 232 ₃ andoutputs data to be output in a first order, fourth order, fifth orderand eighth order as positive values and data to be output in a secondorder, third order, sixth order and seventh order as negative values.The register 234₅ sequentially stores each of eight pieces of dataoutput sequentially from the P₉ coefficient multiplying circuit 232 ₅and outputs data to be output in a first order, third order, fifth orderand seventh order as positive values and data to be output in a secondorder, fourth order, sixth order and eighth order as negative values.The register 234 ₁₄ sequentially stores each of eight pieces of dataoutput sequentially from the P₂ coefficient multiplying circuit 232 ₁₄and outputs data to be output in a first order, fourth order, fifthorder and eighth order as positive values and data to be output in asecond order, third order, sixth order and seventh order as negativevalues.

The register 234 ₂ sequentially stores each of eight pieces of dataoutput in order from the P₁₁ coefficient multiplying circuit 234 ₂ and,in the case of the 16-16 DCT, outputs data to be output in a firstorder, fourth order, sixth order as positive values and data to beoutput in a second order, third order, fifth order, seventh order andeighth order as negative values and, in the case of the 2-8-16 DCT,outputs data to be output in a first order, second order, sixth orderand seventh order as positive values and data to be output in a thirdorder, fourth order fifth order and eighth order as negative values.

The register 234 ₄ sequentially stores each of eight pieces of dataoutput in order from the P₁₃ coefficient multiplying circuit 234 ₄ and,in the case of the 16-16 DCT, outputs data to be output in a firstorder, third order, fifth order and seventh order as positive values anddata to be output in a second order, fourth order, sixth order andeighth order as negative values and, in the case of the 2-8-16 DCT,outputs data to be output in a second order, fourth order, fifth orderand eighth order as positive values and data to be output in a firstorder, third order, sixth order and seventh order as negative values.

The register 234 ₆ sequentially stores each of eight pieces of dataoutput, in order, from the P₅ coefficient multiplying circuit 234 ₆ and,in the case of the 16-16 DCT, outputs data to be output in a firstorder, third order, fifth order and seventh order as positive values anddata to be output in a second order, fourth order, sixth order andeighth order as negative values and, in the case of the 2-8-16 DCT,outputs data to be output in a second order, third order, fifth orderand eighth order as positive values and data to be output in a firstorder, fourth order, sixth order and seventh order as negative values.

The register 234 ₇ sequentially stores each of eight pieces of dataoutput, in order, from the P₁ coefficient multiplying circuit 234 ₇ and,in the case of the 16-16 DCT, outputs data to be output in a firstorder, third order, fifth order and seventh order as positive values anddata to be output in a second order, fourth order, sixth order andeighth order as negative values and, in the case of the 2-8-16 DCT,outputs data to be output in a second order, third order, fifth orderand seventh order as positive values and data to be output in a firstorder, fourth order, sixth order and eighth order as negative values.

The register 234 ₈ sequentially stores each of eight pieces of dataoutput, in order, from the P₁₄/P₇ coefficient multiplying circuit 234 ₈and, in the case of the 16-16 DCT, outputs data to be output in a firstorder, third order, fourth order, fifth order and seventh order aspositive values and data to be output in a second order, sixth order andeighth order as negative values and, in the case of the 2-8-16 DCT,outputs each data to be output as positive values.

The register 234 ₉ sequentially stores each of eight pieces of dataoutput, in order, from the P₁₂/P₁₁ coefficient multiplying circuit 234 ₉and, in the case of the 16-16 DCT, outputs data to be output in a firstorder, second order, seventh order and eighth order as positive valuesand data to be output in a third order to sixth order as negative valuesand, in the case of the 2-8-16 DCT, outputs each data to be output in asecond order, second order, fourth order, sixth order and seventh orderas positive values and data to be output in a third order, fifth orderand eighth order as negative values.

The register 234 ₁₀ sequentially stores each of eight pieces of dataoutput, in order, from the P₁₀/P₃ coefficient multiplying circuit 234 ₁₀and, in the case of the 16-16 DCT, outputs data to be output in a firstorder and third order as positive values and data to be output in asecond order and fourth order to eighth order as negative values and, inthe case of the 2-8-16DCT, outputs each data to be output in a firstorder and fourth order to eighth order as positive values and data to beoutput in a second order and third order as negative values.

The register 234 ₁₁ sequentially stores each of order pieces of dataoutput, in order, from the P₈/P₁₃ coefficient multiplying circuit 234 ₁₁and, in the case of the 16-16 DCT, outputs data to be output in a firstorder and fourth order to sixth order as positive values and data to beoutput in a second order, third order, seventh order and eighth order asnegative values and, in the case of the 2-8-16 DCT, outputs each data tobe output in a first order, fourth order, sixth order and eighth orderas positive values and data to be output in a second order, third order,fifth order and seventh order as negative values.

The register 234 ₁₂ sequentially stores each of eight pieces of dataoutput, in order, from the P₆/P₉ coefficient multiplying circuit 234 ₁₂and, in the case of the 16-16 DCT, outputs data to be output in a firstorder to third order, fifth order and sixth order as positive values anddata to be output in a fourth order, seventh order and eighth order asnegative values and, in the case of the 2-8-16 DCT, outputs each data tobe output in a first order, third order, fifth order and seventh orderas positive values and data to be output in a second order, fourthorder, sixth order and seventh order as negative values.

The register 234 ₁₃ sequentially stores each of eight pieces of dataoutput, in order, from the P₄/P₅ coefficient multiplying circuit 234 ₁₃and, in the case of the 16-16 DCT, outputs data to be output in a firstorder, third order and fifth order to eighth order as positive valuesand data to be output in a second order and fourth order as negativevalues and, in the case of the 2-8-16 DCT, outputs each data to beoutput in a first order, fourth order, fifth order and eighth order aspositive values and data to be output in a second order, third order,sixth order and seventh order as negative values.

The register 234 ₁₅ sequentially stores each of eight pieces of dataoutput, in order, from the P₀/P₁ coefficient multiplying circuit 234 ₁₅and, in the case of the 16-16 DCT, outputs data to be output in a firstorder to fourth order and sixth order to eighth order as positive valuesand data to be output in a fifth order as negative values and, in thecase of the 2-8-16 DCT, outputs each data to be output in a first order,fourth order, fifth order and seventh order as positive values and datato be output in a second order, third order, sixth order and eighthorder as negative values.

The adding circuit 238 ₁ contained in the second adding circuit group237 constitutes an accumulative circuit together with the register 40 ₁constituting the fifth group 239 and with the AND circuit 236 ₁. To oneinput of the AND circuit 236 ₁ is fed data from the register 40 ₁ and,in the case of both the 16-16 DCT and the 2-8-16 DCT, to the other inputof the AND circuit 236 ₁ are signals “0”, “1”, “1”, “0”, “1”, “1” and“1” which are fed from a binary signal string generating circuit (notshown) and correspond to the order from a first operation cycle toeighth operation cycle out of eight operation cycles. An accumulativevalue is output from the resister 40 ₁, which is obtained by addition inthe adding circuit 238 ₁, of data output from the register 234 ₁ and fedto one input of the adding circuit 238 ₁ to data stored in the register40 ₁ on one previous clock and fed, on the next clock, to the otherinput of the adding circuit 238 ₁ through the AND circuit 236 ₁.

The adding circuit 238 ₂ constitutes an accumulative circuit togetherwith the register 40 ₂ and with the AND circuit 236 ₂. To one input ofthe AND circuit 236 ₂ is fed data from the register 40 ₂ and, in thecase of both the 16-16 DCT and the 2-8-16 DCT, to the other input of theAND circuit 236 ₂ are signals “0”, “1”, “1”, “0”, “1”, “1” and “1” whichare fed from a binary signal string generating circuit (not shown) andcorrespond to the order from a first operation cycle to eighth operationcycle out of eight operation cycles. An accumulative value is outputfrom the register 40 ₂, which is obtained by addition, in the addingcircuit 238 ₂, of data output from the register 234 ₂ and register 234 ₃and fed to a first input and second input of the adding circuit 238 ₂ todata stored in the register 40 ₂ on one previous clock and fed, on thenext clock, to the other input of the adding circuit 238 ₂ through theAND circuit 236 ₂.

The adding circuit 238 ₃ constitutes an accumulative circuit togetherwith the register 40 ₃ and with the AND circuit 236 ₃. To one input ofthe AND circuit 236 ₃ is fed data from the register 40 ₃ and, in thecase of both the 16-16 DCT and the 2-8-16 DCT, to the other input of theAND circuit 236 ₃ are signals “0”, “1”, “1”, “0”, “1”, “1” and “1” whichare fed from a binary signal string generating circuit (not shown) andcorrespond to the order from a first operation cycle to eighth operationcycle out of eight operation cycles. An accumulative value is outputfrom the register 40 ₃, which is obtained by addition, in the addingcircuit 238 ₂, of data output from the register 234 ₄ to register 234 ₇and fed to the first inputs of the adding circuit 238 ₃ to data storedin the register 40 ₃ on one previous clock and fed, on the next clock,to the fifth input of the adding circuit 238 ₃ through the AND circuit236 ₃.

The adding circuit 238 ₄, in the case of the 16-16 DCT, performs addingoperations on data output from the register 234 ₈ to register 234 ₁₅ andstores the result into the register 40 ₄, and in the case of the 2-8-16DCT, constitutes an accumulative circuit together with the register 234₈ to register 234 ₁₅ and with the AND circuit 236 ₅. That is, to oneinput of the AND circuit 236 ₅ is fed data output from the register 40 ₅and to the other input of the AND circuit 236 ₅, in the case of the16-16 DCT, is fed a signal “0” in a first operation cycle to eighthoperation cycle out of eight operation cycles by a binary stringgenerating circuit (not shown) and, in the case of the 2-8-16 DCT, arefed signals “0”, “1”, “0”, “1”, “0”, “1”, “0” and “1” which correspondto the order from a first operation cycle to eighth operation cycle outof eight operation cycles and are fed by the binary string generatingcircuit (not shown).

To one input of the AND circuit 236 ₇ is fed data from the register 234,to one input of the AND circuit 236 ₈ is fed data from the register 234and to one input of the AND circuit 236 ₉ is fed data from the register30 ₁₀. To the other input of each of the AND circuit 236 ₇, AND circuit236 ₈ and AND circuit 236 ₉ is fed a signal “0” in a first operationcycle to eighth operation cycle out of eight operation cycles by thebinary string generating circuit (not shown) in the case of the 16-16DCT and is fed a signal “1” in a first operation cycle to eighthoperation cycle out of eight operation cycles by the binary stringgenerating circuit (not shown).

In the case of the 16-16 DCT, data output sequentially from each of theregister 234 ₈ to register 234 ₁₅ in every operation cycle out of eightoperation cycles is fed, in every operation cycle, to one of a firstinput to eighth input of the adding circuit 238 ₄ and undergoes anadding operation and then the resulting data is stored sequentially intothe register 40 ₄, while, in the case of the 2-8-16 DCT, data outputsequentially from each of the register 234 ₁₁ to register 234 ₁₅ inevery operation cycle out of the eight operation cycles and input to oneof a fourth input to eighth input of the adding circuit 238 ₄ is addedto data stored in one previous clock into the register 40 ₄ and is fed,on the next clock, to a ninth input of the adding circuit 238 ₄ throughthe AND circuit 236 ₅ in the adding circuit 238 ₄ and the resulting datais output from the register 40 ₄.

Next, operations of the 16-16 DCT and the 2-4-8 DCT of the firstembodiment will be described by referring to FIGS. 13 to 14. First,operations of the 16-16 DCT will be explained below.

Each of sixteen pieces of data F₀ to data F₁₅ (input data for DCT)contained in each line constituting a block composed of 16×16 pieces ofdata transmitted sequentially from the MUX 212 is stored into each ofthe register 14 ₁ to register 14 ₁₅ contained in the first registergroup 213. That is, data f₀ is stored into the register 14 ₁constituting the first register group 213, data f₁₅ into the register 14₂, data f₁ into the register 14 ₃, data f₁₄ into the register 14 ₄, dataf₂ into the register 14 ₅, data f₁₃ into the register 14 ₆, data f₃ intothe register 14 ₇, data f₁₂ into the register 14 ₈, data f₄ into theregister 14 ₉, data f₁₁ into the register 14 ₁₀, data f₅ into theregister 14 ₁₁ data f₁₀ into the register 14 ₁₂, data f₆ into theregister 14 ₁₃, data f₉ into the register 14 ₁₄, data f₇ into theregister 14 ₁₅ and f₈ into the register 16.

Thus, when each of the sixteen pieces of picture element data is storedinto each of the register 14 ₁ to register 14 ₁₆, data f₀+f₁₅=e₀ isoutput from the adding circuit 18 ₁, data f₁+f₁₄=e₁ from the addingcircuit 18 ₂, data f₂+f₁₃=e₂ from the adding circuit 18 ₃, dataf₃+f₁₂=e₃ from the adding circuit 18 ₄, data f₄+f₁₁=e₄ from the addingcircuit 18 ₅, data f₅+f₁₀=e₅ from the adding circuit 18 ₆, data f₆+f₉=e₆from the adding circuit 18 ₇, and data f₇+f₈=e₇ from the adding circuit18 ₈.

Data f₀−f₁₅=e₈ is output from the subtracting circuit 20 ₁, dataf₁−f₁₄=e₉ from the subtracting circuit 20 ₂, data f₂−f₁₃=e₁₀ from thesubtracting circuit 20 ₃, data f₃−f₁₂=e₁₁ from the subtracting circuit20 ₄, data f₄−f₁₁=e₁₂ from the subtracting circuit 20 ₅, data f₅−f₁₀=e₁₃from the subtracting circuit 20 ₆, data f₆−f₉=e₁₄ from the subtractingcircuit 20 ₇ and data f₆−f₉=e₁₄ from the subtracting circuit 20 ₇.

Data e₀ output from the adding circuit 18 ₁ is stored in the register 22₁, data e₁ output from the adding circuit 18 ₂ is stored in the register22 ₂, data e₂ output from the adding circuit 18 ₃ is stored in theregister 22 ₃, data e₃ output from the adding circuit 18 ₄ is stored inthe register 22 ₄, data e₄ output from the adding circuit 18 ₅ is storedin the register 22 ₅, data e₅ output from the adding circuit 18 ₆ isstored in the register 22 ₆, data e₆ output from the adding circuit 18 ₇is stored in the register 22 ₇ and data e₇ output from the addingcircuit 18 ₈ is stored in the register 22 ₈.

Data e₈ output from the subtracting circuit 20 ₁ is stored in theregister 22 ₉, data e₉ output from the subtracting circuit 20 ₂ isstored in the register 22 ₁₀, data e₁₀ output from the subtractingcircuit 20 ₃ is stored in the register 22 ₁₁, data e₁₁ output from thesubtracting circuit 20 ₄ is stored in the register 22 ₁₂, data e₁₂output from the subtracting circuit 20 ₅ is stored in the register 22₁₃, data e₁₃ output from the subtracting circuit 20 ₆ is stored in theregister 22 ₁₄, data e₁₄ output from the subtracting circuit 20 ₇ isstored in the register 22 ₁₅ and data e₁₅ output from the subtractingcircuit 20 ₈ is stored in the register 22 ₁₆.

Data e₀ to data e₇ output from the adding circuit 18 ₁ to adding circuit18 ₈ are input to the MUX 224 ₁ to MUX 224 ₈ through the register 22 ₁to register 22 ₈, the following data are output from the MUX 224 ₁, toMUX 224 ₈. Eight pieces of data e₀, e₃, e₄, e₇, e₀, e₃, e₄ and e₇ outputfrom the MUX 224 ₁ sequentially in every operation cycle out of eightoperation cycles are fed to the adding/subtracting circuits 226 ₁ andeight pieces of data e₁, e₂, e₅, e₆, e₁, e₂, e₅ and e₆ output from theMUX 224 ₂ sequentially in every operation cycle out of eight operationcycles are fed to the adding/subtracting circuits 226 ₁ and then datae₀+e₁, data e₃+e₂, data e₄+e₅, data e₇+e₆, data e₀−e₁, data e₃−e₂, datae₄−e₅, and data e₇−e₆ are output sequentially from theadding/subtracting circuit 226 ₁ in every operation cycle out of eightoperation cycles and are stored in the register 30 ₁.

Data e₀, e₁, e₂, e₃, e₄, e₅, e₆ and e₇ output from the register 22 ₁ toregister 22 ₈ in every operation cycle out of eight operation cycles areselected by the MUX 224 ₃ in every operation cycle out of eightoperation cycles and data e₀, e₃, e₄, e₇, e₁, e₂, e₅ and e₆ are outputsequentially from the MUX 224 ₃ and stored in the register 30 ₂. Datae₀, e₁, e₂, e₃, e₄, e₅, e₆ and e₇ output from the register 22 ₁ toregister 22 ₈ in every operation cycle out of eight operation cycles areselected by the MUX 224 ₄ in every operation cycle out of eightoperation cycles and data e₁, e₂, e₅, e₆, e₀, e₃, e₄ and e₇ are outputsequentially from the MUX 224 ₃ and stored in the register 30 ₃. Datae₀, e₁, e₂, e₃, e₄, e₅, e₆ and e₇ output from the register 22 ₁ toregister 22 ₈ in every operation cycle out of eight operation cycles areselected by the MUX 224 ₅ in every operation cycle out of eightoperation cycles and data e₀, e₇, e₅, e₂, e₆, e₁, e₄ and e₃ are outputsequentially from the MUX 224 ₅ and stored in the register 30 ₄. Datae₀, e₁, e₂, e₃, e₄, e₅, e₆ and e₇ output from the register 22 ₁ toregister 22 ₈ in every operation cycle out of eight operation cycles areselected by the MUX 224 ₆ in every operation cycle out of eightoperation cycles and data e₁, e₆, e₀, e₆, e₃, e₄, e₂ and e₅ are outputsequentially from the MUX 224 ₆ and stored in the register 30 ₅. Datae₀, e₁, e₂, e₃, e₄, e₅, e₆ and e₇ output from the register 22 ₁ toregister 22 ₈ in every operation cycle out of eight operation cycles areselected by the MUX 224 ₇ in every operation cycle out of eightoperation cycles and data e₂, e₅, e₃, e₄, e₀, e₇, e₆ and e₁ are outputsequentially from the MUX 224 ₆ and stored in the register 30 ₆.

Data e₀, e₁, e₂, e₃, e₄, e₅, e₆ and e₇ output from the register 22 ₁ toregister 22 ₈ in every operation cycle out of eight operation cycles areselected by the MUX 224 ₈ in every operation cycle out of eightoperation cycles and data e₃, e₄, e₆, e₁, e₂, e₅, e₀ and e₇ are outputsequentially from the MUX 224 ₆ and stored in the register 30 ₇.

Data e₈, e₉, e₁₀, e₁₁, e₁₂, e₁₃, e₁₄ and e₁₅ output from the register 22₉ to register 22 ₁₂ in every operation cycle out of eight operationcycles are selected by the MUX 224 ₉ in every operation cycle out ofeight operation cycles and data e₈, e₁₃, e₁₄, e₁₂, e₁₁, e₉, e₁₀ and e₁₅are output sequentially from the MUX 224 ₆ and stored through the MUX 28₁ into the register 30 ₈. Data e₈, e₉, e₁₀, e₁₁, e₁₂, e₁₃, e₁₄ and e₁₅output from the register 22 ₉ to register 22 ₁₂ in every operation cycleout of eight operation cycles are selected by the MUX 224 ₁₀ in everyoperation cycle out of eight operation cycles and data e₉, e₈, e₁₁, e₁₀,e₁₃, e₁₂, e₁₅ and e₁₄ are output sequentially from the MUX 224 ₁₀ andstored in the register 30 ₉. Data e₈, e₉, e₁₀, e₁₁, e₁₂, e₁₃, e₁₄ ande₁₅ output from the register 22 ₉ to register 22 ₁₂ in every operationcycle out of eight operation cycles are selected by the MUX 224 ₁₁ inevery operation cycle out of eight operation cycles and data e₁₀, e₁₂,e₈, e₁₄, e₉, e₁₅, e₁₁ and e₁₃ are output sequentially from the MUX 224₁₁ and stored in the register 30 ₁₀. Data e₈, e₉, e₁₀, e₁₁, e₁₂, e₁₃,e₁₄ and e₁₅ output from the register 22 ₉ to register 22 ₁₂ in everyoperation cycle out of eight operation cycles are selected by the MUX224 ₁₂ in every operation cycle out of eight operation cycles and datae₁₁, e₁₄, e₁₀, e₈, e₁₅, e₁₃, e₉ and e₁₂ are output sequentially from theMUX 224 ₁₂ and stored in the register 30 ₁₁. Data e₈, e₉, e₁₀, e₁₁, e₁₂,e₁₃, e₁₄ and e₁₅ output from the register 22 ₉ to register 22 ₁₂ inevery operation cycle out of eight operation cycles are selected by theMUX 224 ₁₃ in every operation cycle out of eight operation cycles anddata e₁₂, e₉, e₁₃, e₁₅, e₈, e₁₀, e₁₄ and e₁₁ are output sequentiallyfrom the MUX 224 ₁₃ and stored in the register 30 ₁₂. Data e₈, e₉, e₁₀,e₁₁, e₁₂, e₁₃, e₁₄ and e₁₅ output from the register 22 ₉ to register 22₁₂ in every operation cycle out of eight operation cycles are selectedby the MUX 224 ₁₄ in every operation cycle out of eight operation cyclesand data e₁₃, e₁₁, e₁₅, e₉, e₁₄, e₈, e₁₂ and e₁₀ are output sequentiallyfrom the MUX 224 ₁₄ and stored in the register 30 ₁₃. Data e₈, e₉, e₁₀,e₁₁, e₁₂, e₁₃, e₁₄ and e₁₅ output from the register 22 ₉ to register 22₁₂ in every operation cycle out of eight operation cycles are selectedby the MUX 224 ₁₅ in every operation cycle out of eight operation cyclesand data e₁₄, e₁₅, e₁₂, e₁₃, e₁₀, e₁₁, e₈ and e₉ are output sequentiallyfrom the MUX 224 ₁₅ and stored through the MUX 282 into the register 30₁₄. Data e₁, e₃, e₅, e₇, e₉, e₁₁, e₁₃ and e₁₅ output from the register22 ₉ to register 22 ₁₂ in every operation cycle out of eight operationcycles are selected by the MUX 224 ₁₆ in every operation cycle out ofeight operation cycles and data e₁₅, e₁₀, e₉, e₁₁, e₁₂, e₁₄, e₁₃ and e₈are output sequentially from the MUX 224 ₁₆ and stored in the register30 ₁₅.

Each piece of data output from the register 30 ₁ to register 30 ₇ inevery operation cycle out of eight operation cycles is multiplied byeach of corresponding fixed coefficients P₇, P₁₁, P₁₃, P₃, P₉, P₅ and P₁in every operation cycle out eight operation cycles in each of thecorresponding fixed coefficient multiplying circuits 232 ₁ to 232 ₂ andis stored into each of the corresponding register 234 ₁ to register 234₇. That is, each piece of data stored sequentially into the register 234₁ undergoes adding operations in every operation cycle out of eightoperation cycles in the adding circuit 238 ₁ and the resulting data isstored into the register 40 ₁.

Data (e₀+e₁) P₇ is output from the adding circuit 238 ₁ in a firstoperation cycle out of eight operation cycles, data (e₀+e₁+e₃+e₂) P₇ ina second operation cycle out of the eight operation cycles, data(e₀+e₁+e₃+e₂+e₄+e₅) P₇ in a third operation cycle out of the eightoperation cycles, data (e₀+e₁+e₃+e₂+e₄+e₅+e₇+e₆) P₇ in a fourthoperation cycle out of the eight operation cycles, data (e₀−e₁) P₇ in afifth operation cycle out of the eight operation cycles, data(e₀−e₁+e₃−e₂) P₇ in a sixth operation cycle out the eight operationcycles, data (e₀−e₁+e₃−e₂+e₄−e₅) P₇ in a seventh operation cycle out ofthe eight operation cycles and data (e₀−e₁+e₃−e₂+e₄−e₅+e₇−e₆) P₇ in aeighth operation cycle out of the eight operation cycles. Out of dataoutput from the adding circuit 238 ₁ in every operation cycle out ofeight operation cycles, data output in the fourth operation cycle andeighth operation cycle represent operation value F₀ and operation valueF₈ expressed in the equation (65) which are shown as F₀ and F₈ on alower right of an output line of the register 40 ₁ and data output inthe first operation cycle to third operation cycle and fifth operationcycle to seventh operation cycle represent undefined values which areshown by asterisk marks “*” on the lower right of the output line of theregister 40 ₁ in FIG. 14.

Each piece of data stored sequentially into the register 234 ₂ andregister 234 ₃ undergoes adding operations in every operation cycle outof eight operation cycles in the adding circuit 238 ₂ and the resultingdata is stored into the register 40 ₂.

Data e₀P₁₁+e₁P₃ is output from the adding circuit 238 ₂ in a firstoperation cycle out of the eight operation cycles, datae₀P₁₁+e₁P₃−e₃P₁₁−e₂P₃ in a second operation cycle out of the eightoperation cycles, data e₀P₁₁+e₁P₃−e₃P₁₁−e₂P₃−e₄P₁₁−e₅P₃ in a thirdoperation cycle out of the eight operation cycles, datae₀P₁₁+e₁P₃−e₃P₁₁−e₂P₃−e₄P₁₁−e₅P₃+e₇P₁₁+e₆P₃ in a fourth operation cycleout the eight operation cycles, data −e₁P₁₁+e₀P₃ in a fifth operationcycle out of the eight operation cycles, data −e₁P₁₁+e₀P₃+e₂P₁₁−e₃P₃ ina sixth operation cycle out of the eight operation cycles, data−e₁P₁₁+e₀P₃+e₂P₁₁−e₃P₃−e₅P₁₁−e₄P₃ in a seventh operation cycle out ofthe eight operation cycles and data−e₁P₁₁+e₀P₃+e₂P₁₁−e₃P₃−e₅P₁₁−e₄P₃−e₆P₁₁+e₇P₃ in an eighth operationcycle out of the eight operation cycles.

Out of data output from the adding circuit 238 ₂ in every operationcycle out of eight operation cycles, data output in the fourth operationcycle and eighth operation cycle represent operation value F₂ andoperation value F₆ expressed in the equation (65) which are shown as F₂and F₆ on a lower right of an output line of the register 40 ₂ and dataoutput in the first operation cycle to third operation cycle and fifthoperation cycle to seventh operation cycle represent undefined valueswhich are shown by asterisk marks “*” on the lower right of the outputline of the register 40 ₂ in FIG. 14.

Each piece of data stored sequentially into the register 234 ₄ toregister 234 ₇ undergoes adding operations in every operation cycle outof eight operation cycles in the adding circuit 238 ₃ and the resultingdata is stored into the register 40 ₃.

Data e₀P₁₃+e₁P₉+e₂P₅+e₃P₁ is output from the adding circuit 238 ₃ in afirst operation cycle out of the eight operation cycles, datae₀P₁₃+e₁P₉+e₂P₅+e₃P₁−e₇P₁₃−e₆P₉−e₅P₅−e₄P₁ in a second operation cycleout of the eight operation cycles, data e₅P₁₃+e₀P₉+e₃P₅+e₅P₁ in a thirdoperation cycle out of the eight operation cycles, datae₅P₁₃+e₀P₉+e₃P₅+e₆P₁−e₂P₁₃−e₆P₉−e₄P₅−e₁P₁ in a fourth operation cycleout the eight operation cycles, data e₆P₁₃+e₂P₉+e₀P₅+e₃P₁ in a fifthoperation cycle out of the eight operation cycles, datae₆P₁₃+e₂P₉+e₀P₅+e₃P₁−e₁P₁₃−e₄P₉−e₇P₅−e₅P₁ in a sixth operation cycle outof the eight operation cycles, data e₄P₁₃+e₂P₉−e₁P₅+e₀P₁ in a seventhoperation cycle out of the eight operation cycles and datae₄P₁₃+e₂P₉−e₁P₅+e₀P₁−e₃P₁₃−e₅P₉+e₆P₅−e₇P₁ in an eighth operation cycleout of the eight operation cycles.

Out of data output from the adding circuit 238 ₃ in every operationcycle out of eight operation cycles, data output in the second operationcycle, fourth operation cycle, sixth operation cycle and eighthoperation cycle represent operation value F₁₀, operation value F₁₄,operation value F₄ and operation value F₁₂ expressed in the equation(65) which are shown as F₁₀, F₁₄, F₄ and F₁₂ on a lower right of anoutput line of the register 40 ₃ and data output in the first operationcycle, third operation cycle, fifth operation cycle and seventhoperation cycle represent undefined values which are shown by asteriskmarks “*” on the lower right of the output line of the register 40 ₃ inFIG. 14.

Each piece of data stored sequentially into the register 234 ₈ toregister 234 ₁₅ undergoes adding operations in every operation cycle outof eight operation cycles in the adding circuit 238 ₄ and the resultingdata is stored into the register 40 ₄.

Data e₈P₁₄+e₉P₁₂+e₁₀P₁₀+e₁₁P₈+e₁₂P₆+e₁₃P₄+e₁₄P₂+e₁₅P₀ is output from theadding circuit 238 ₄ in a first operation cycle out of the eightoperation cycles, data −e₁₃P₁₄+e₈P₁₂−e₁₂P₁₀−e₁₄P₈+e₉P₆−e₁₁P₄−e₁₅P₂+e₁₀P₀in a second operation cycle out of the eight operation cycles, datae₁₄P₁₄−e₁₁P₁₂+e₈P₁₀−e₁₀P₈+e₁₃P₆+e₁₅P₄−e₁₂P₂+e₉P₀ in a third operationcycle out of the eight operation cycles, datae₁₂P₁₄−e₁₀P₁₂−e₁₄P₁₀+e₈P₈−e₁₅P₆−e₉P₄+e₁₃P₂+e₁₁P₀ in a fourth operationcycle out the eight operation cycles, datae₁₁P₁₄−e₁₃P₁₂−e₉P₁₀+e₁₅P₈+e₈P₆+e₁₄P₄−e₁₀P₂−e₁₂P₀ in a fifth operationcycle out of the eight operation cycles, data−e₉P₁₄−e₁₂P₁₂−e₁₅P₁₀+e₁₃P₈+e₁₀P₆+e₈P₄+e₁₁P₂+e₁₄P₀ in a sixth operationcycle out of the eight operation cycles, datae₁₀P₁₄+e₁₅P₁₂−e₁₁P₁₀−e₉P₈−e₁₄P₆+e₁₂P₄+e₈P₂+e₁₃P₀ in seventh operationcycle out of the eight operation cycles and data−e₁₅P₁₄+e₁₄P₁₂−e₁₃P₁₀−e₁₂P₈−e₁₁P₆+e₁₀P₄−e₉P₂+e₈P₀ in an eight operationcycle out of the eight operation cycles. Data output from the addingcircuit 238 ₄ in every operation cycle out the eight operation cyclesrepresent the operation values F₁, F₃, F₅, F₇, F₉, F₁₁, F₁₃ and F₁₅ inthe equation (65) respectively which are shown as F₁, F₃, F₅, F₇, F₉,F₁₁, F₁₃ and F₁₅ in a lower right of an output line of the register 40 ₄in FIG. 14.

By completing the above arithmetic operations, the primary 16-16 DCT oneight pieces of data in one line constituting the 16×16 data block isterminated. The same primary 16-16 DCT as described above is performedon each of lines subsequent to a next line constituting the 16×16 datablock and thereafter, and the primary 16-16 DCT on all eight linesconstituting the 16×16 data block is terminated in the similar manner.After the completion of the primary 16-16 DCT on the all eight lines, asecondary 16-16 DCT is performed on each string of eight data stringsconstituting the16×16 data block. The transformation coefficient dataobtained by completing the secondary 16-16 DCT is used for compressionof input 16×16 picture data. Thus, transmission of compressed pictureelement data is made possible by using the transformation coefficientdata obtained by performing the primary 16-16 DCT and secondary 16-16DCT on the 16×16 picture element data within an image to be transmittedfor compression of the 16×16 picture element data block.

Next, operations of the 2-8-16 DCT will be described. Each of sixteenpieces of data F₀ to data F₁₅ (input data for DCT) of each lineconstituting 16×16 data block transmitted sequentially from the MUX 212is stored into each of the register 14 ₁ to register 14 ₁₅ contained inthe first register group 213.

When each of the sixteen pieces of picture element data f₀ to pictureelement data f₁₅ is stored into each of the register 14 ₁ to register 14₁₆, data f₀+f₁=g₀ is output from the adding circuit 18 ₂, data f₂+f₃=g₁from the adding circuit 18 ₂, data f₄+f₅=g₂ from the adding circuit 18₃, data f₆+f₇=g₃ from the adding circuit 18 ₄, data f₈+f₉=g₄ from theadding circuit 18 ₅, data f₁₀+f₁₁=g₅ from the adding circuit 18 ₆, dataf₁₂+f₁₃=g₆ from the adding circuit 18 ₇ and data f₁₄+f₁₅=g₇ from theadding circuit 18 ₈. Data f₀−f₁=g₈ is output from the subtractingcircuit 20 ₁, data f₂−f₃=g₉ from the subtracting circuit 20 ₂, dataf₄−f₅=g₁₀ from the subtracting circuit 20 ₃, data f₆−f₇=g₁₁ from thesubtracting circuit 20 ₄, data f₈−f₉=g₁₂ from the subtracting circuit 20₅, data f₁₀−f₁₁=g₁₁ from the subtracting circuit 20 ₆, data f₁₂−f₁₃=g₁₄from the subtracting circuit 20 ₇ and f₁₄−f₁₅=g₁₅ from the subtractingcircuit 20 ₈.

Data g₀ output from the adding circuit 18 ₁ is stored into the register22 ₁, data g₁ output from the adding circuit 18 ₂ is stored into theregister 22 ₂, data g₂ output from the adding circuit 18 ₃ is storedinto the register 22 ₃, data g₃ output from the adding circuit 18 ₄ isstored into the register 22 ₄, data g₄ output from the adding circuit 18₅ is stored into the register 22 ₅, data g₅ output from the addingcircuit 18 ₆ is stored into the register 22 ₅, data g₆ output from theadding circuit 18 ₇ is stored into the register 22 ₆ and data g₇ outputfrom the adding circuit 18 ₈ is stored into the register 22 ₈.

Data g₈ output from the subtracting circuit 20 ₁ is stored into theregister 22 ₉, data g₉ output from the subtracting circuit 20 ₂ isstored into the register 22 ₁₀, data g₁₀ output from the subtractingcircuit 20 ₃ is stored into the register 22 ₁₁, data g₁₁ output from thesubtracting circuit 20 ₅ is stored into the register 22 ₁₂, data g₁₂output from the subtracting circuit 20 ₅ is stored into the register 22₁₃, data g₁₃ output from the subtracting circuit 20 ₆ is stored into theregister 22 ₁₄, data g₁₄ output from the subtracting circuit 20 ₈ isstored into the register 22 ₁₅ and data g₁₅ output from the subtractingcircuit 20 ₈ is stored into the register 22 ₁₆.

When data g₀ to data g₇ output from the adding circuit 18 ₁ to addingcircuit 18 ₈ are input to the MUX 224 ₁ to MUX 224 ₈ through theregister 22 ₁ to register 22 ₈, the following data are output from theMUX 224 ₁ to MUX 224 ₈. When eight pieces of data g₀, g₃, g₄, g₇, g₀,g₃, g₄ and g₇ output sequentially from the MUX 224 ₁ in every operationcycle out of eight operation cycles are fed to the adding/subtractingcircuit 226 ₁ and eight pieces of data g₁, g₂, g₅, g₆, g₁, g₂, g₅ and g₆are fed to the adding/subtracting circuit 226 ₁, data g₀+g₁, data g₃+g₂,data g₅+g₄, data g₇+g₆, data g₁−g₀, data g₃−g₂, data g₅−g₄ and datag₇−g₆ are output sequentially and stored into the register 30 ₁.

Each of data g₀, g₃, g₄, g₇, g₀, g₃, g₄ and g₇ output from the register22 ₁ to register 22 ₈ in every operation cycle out of eight operationcycles is selected by the MUX 224 ₃ in every operation cycle out of theeight operation cycles and each of data g₀, g₇, g₃, g₄, g₁, g₂, g₅ andg₆ is output sequentially from the MUX 224 ₃ and stored into theregister 30 ₂. Each of data g₀, g₁, g₂, g₃, g₄, g₅, g₆ and g₇ outputfrom the register 22 ₁ to register 22 ₈ in every operation cycle out ofeight operation cycles is selected by the MUX 224 ₄ in every operationcycle out of the eight operation cycles and each of data g₁, g₂, g₅, g₆,g₀, g₃, g₄ and g₇ is output sequentially from the MUX 224 ₄ and storedinto the register 30 ₃. Each of data g₀, g₁, g₂, g₃, g₄, g₅, g₆ and g₇output from the register 22 ₁ to register 22 ₈ in every operation cycleout of eight operation cycles is selected by the MUX 224 ₅ in everyoperation cycle out of the eight operation cycles and each of data g₂,g₅, g₁, g₆, g₀, g₇, g₃ and g₄ is output sequentially from the MUX 224 ₄and stored into the register 30 ₄. Each of data g₀, g₁, g₂, g₃, g₄, g₅,g₆ and g₇ output from the register 22 ₁ to register 22 ₈ in everyoperation cycle out of eight operation cycles is selected by the MUX 224₆ in every operation cycle out of the eight operation cycles and each ofdata g₀, g₇, g₃, g₄, g₁, g₆, g₂ and g₅ is output sequentially from theMUX 224 ₄ and stored into the register 30 ₅. Each of data g₀, g₁, g₂,g₃, g₄, g₅, g₆ and g₇ output from the register 22 ₁ to register 22 ₈ inevery operation cycle out of eight operation cycles is selected by theMUX 224 ₇ in every operation cycle out of the eight operation cycles andeach of data g₃, g₄, g₀, g₇, g₂, g₅, g₁ and g₆ is output sequentiallyfrom the MUX 224 ₇ and stored into the register 30 ₆. Each of data g₀,g₁, g₂, g₃, g₄, g₅, g₆ and g₇ output from the register 22 ₁ to register22 ₈ in every operation cycle out of eight operation cycles is selectedby the MUX 224 ₈ in every operation cycle out of the eight operationcycles and each of data g₁, g₆, g₂, g₅, g₃, g₄, g₀ and g₇ is outputsequentially from the MUX 224 ₈ and stored into the register 30 ₇. Eachof data g₈, g₉, g₁₀, g₁₁, g₁₂, g₁₃, g₁₄ and g₁₅ output from the register22 ₉ to register 22 ₁₆ in every operation cycle out of eight operationcycles is selected by the MUX 224 ₉ in every operation cycle out of theeight operation cycles and each of data g₈, g₁₁, g₁₂, g₁₅, g₈, g₁₁, g₁₂and g₁₅ is output sequentially from the MUX 224 ₉ and stored into theregister 30 ₈. Each of data g₈, g₉, g₁₀, g₁₁, g₁₂, g₁₃, g₁₄ and g₁₅output from the register 22 ₉ to register 22 ₁₆ in every operation cycleout of eight operation cycles is selected by the MUX 224 ₁₀ in everyoperation cycle out of the eight operation cycles and each of data g₈,g₁₅, g₁₁, g₁₂, g₉, g₁₀, g₁₃ and g₁₄ is output sequentially from the MUX224 ₁₀ and stored into the register 30 ₉. Each of data g₈, g₉, g₁₀, g₁₁,g₁₂, g₁₃, g₁₄ and g₁₅ output from the register 22 ₉ to register 22 ₁₆ inevery operation cycle out of eight operation cycles is selected by theMUX 224 ₁₀ in every operation cycle out of the eight operation cyclesand each of data g₈, g₁₅, g₁₁, g₁₂, g₉, g₁₀, g₁₃ and g₁₄ is outputsequentially from the MUX 224 ₁₀ and stored into the register 30 ₉. Eachof data g₈, g₉, g₁₀, g₁₁, g₁₂, g₁₃, g₁₄ and g₁₅ output from the register22 ₉ to register 22 ₁₆ in every operation cycle out of eight operationcycles is selected by the MUX 224 ₁₁ in every operation cycle out of theeight operation cycles and each of data g₉, g₁₀, g₁₃, g₁₄, g₈, g₁₁, g₁₂and g₁₅ is output sequentially from the MUX 224 ₁₁ and stored into theregister 30 ₁₀. Each of data g₈, g₉, g₁₀, g₁₁, g₁₂, g₁₃, g₁₄ and g₁₅output from the register 22 ₉ to register 22 ₁₆ in every operation cycleout of eight operation cycles is selected by the MUX 224 ₁₂ in everyoperation cycle out of the eight operation cycles and each of data g₈,g₁₅, g₁₀, g₁₃, g₉, g₁₄, g₁₁ and g₁₂ is output sequentially from the MUX224 ₁₁ and stored into the register 30 ₁₁. Each of data g₈, g₉, g₁₀,g₁₁, g₁₂, g₁₃, g₁₄ and g₁₅ output from the register 22 ₉ to register 22₁₆ in every operation cycle out of eight operation cycles is selected bythe MUX 224 ₁₃ in every operation cycle out of the eight operationcycles and each of data g₉, g₁₄, g₈, g₁₅, g₁₁, g₁₂, g₁₀ and g₁₃ isoutput sequentially from the MUX 224 ₁₁ and stored into the register 30₁₂. Each of data g₈, g₉, g₁₀, g₁₁, g₁₂, g₁₃, g₁₄ and g₁₅ output from theregister 22 ₉ to register 22 ₁₆ in every operation cycle out of eightoperation cycles is selected by the MUX 224 ₁₄ in every operation cycleout of the eight operation cycles and each of data g₁₀, g₁₃, g₁₁, g₁₂,g₉, g₁₅, g₈ and g₁₄ is output sequentially from the MUX 224 ₁₁ andstored into the register 30 ₁₃.

Each of data g₈, g₉, g₁₀, g₁₁, g₁₂, g₁₃, g₁₄ and g₁₅ output from theregister 22 ₉ to register 22 ₁₆ in every operation cycle out of eightoperation cycles is not selected by the MUX 224 ₁₅ in every operationcycle out of the eight operation cycles and data “0” is selected eighttimes and output sequentially and then stored into the register 30 ₁₄.Each of data g₈, g₉, g₁₀, g₁₁, g₁₂, g₁₃, g₁₄ and g₁₅ output from theregisters 22 ₉ to 22 ₁₆ in every operation cycle out of eight operationcycles is selected by the MUX 224 ₁₆ in every operation cycle out of theeight operation cycles and each of data g₁₁, g₁₂, g₉, g₁₄, g₁₀, g₁₃, g₈and g₁₅ is output sequentially from the MUX 224 ₁₆ and stored into theregister 30 ₁₅.

Each of data output from the register 30 ₁ to register 30 ₇ in everyoperation cycle out of eight operation cycles is multiplied P₉, P₅ andP₁ in each of the corresponding fixed coefficient multiplying circuit232 ₁ to corresponding fixed coefficient multiplying circuit 232 ₇ andthen stored into each of the corresponding register 234 ₁ tocorresponding register 234 ₇. Each of data stored sequentially into theregister 234 ₁ undergoes adding operations in the adding circuit 238 ₁in every operation cycle out of eight operation cycles and is storedinto the register 40 ₁.

Data (g₀+g₁) P₇ is output from the adding circuit 238 ₁ in a firstoperation cycle out of eight operation cycles, data (g₀+g₁+g₃+g₂) P₇ ina second operation cycle out of the eight operation cycles, data(g₀+g₁+g₃+g₂+g₄+g₅) P₇ in a third operation cycle out of the eightoperation cycles, data (g₀+g₁+g₃+g₂+g₄+g₅+g₇+g₆) P₇ in a fourthoperation cycle out of the eight operation cycles, data (g₀−g₁) P₇ in afifth operation cycle out of the eight operation cycles, data(g₀−g₁+g₃−g₂) P₇ in a sixth operation cycle out of the eight operationcycles, data (g₀−g₁+g₃−g₂+g₄−g₅) P₇ in a seventh operation cycle out ofthe eight operation cycles and data (g₀−g₁+g₃−g₂+g₄−g₅+g₇−g₆) P₇ in aeighth operation cycle out of the eight operation cycles. Out of dataoutput from the adding circuit 238 ₁ in every operation cycle out of theeight operation cycles, data output in the fourth operation cycle andeighth operation cycle represent operation value F₀ and operation valueF₄ expressed in the equation (66) which are shown as F₀ and F₄ on alower left of the output line of the register 40 ₁ and data output inthe first operation cycle to third operation cycle and fifth operationcycle to seventh operation cycle represent undefined values which areshown by asterisk marks “*” on the lower left of the output line of theregister 40 ₁ in FIG. 14.

Each of data stored sequentially into the register 234 ₂ and register234 ₃ undergoes adding operations in the adding circuit 238 ₂ in everyoperation cycle out of eight operation cycles and is stored into theregister 40 ₂.

Data g₀P₁₁+g₁P₃ is output from the adding circuit 238 ₂ in a firstoperation cycle out of eight operation cycles, datag₀P₁₁+g₁P₃+g₇P₁₁−g₂P₃ in a second operation cycle out of the eightoperation cycles, data g₀P₁₁+g₁P₃+g₇P₁₁−g₂P₃−g₃P₁₁−g₅P₃ in a thirdoperation cycle out of the eight operation cycles, datag₀P₁₁+g₁P₃+g₇P₁₁−g₂P₃−g₃P₁₁−g₅P₃−g₄P₁₁+g₆P₃ in a fourth operation cycleout of the eight operation cycles, data −g₁P₁₁+g₀P₃ in a fifth operationcycle out of the eight operation cycles, data −g₁P₁₁+g₀P₃+g₂P₁₁−g₃P₃ ina sixth operation cycle out of the eight operation cycles, data−g₁P₁₁+g₀P₃+g₂P₁₁−g₃P₃+g₅P₁₁−g₄P₃ in a seventh operation cycle out ofthe eight operation cycles and data−g₁P₁₁+g₀P₃+g₂P₁₁−g₃P₃+g₅P₁₁−g₄P₃−g₆P₁₁+g₇P₃ in an eighth operationcycles. Out of data output from the adding circuit 238 ₂ in everyoperation cycle out of eight operation cycles, data output in the fourthoperation cycle and eighth operation cycle represent operation value F₀and operation value F₄ expressed in the equation (66) which are shown asF₂ and F₆ on a lower left of the output line of the register 40 ₂ anddata output in the first operation cycle to third operation cycle andfifth operation cycle to seventh operation cycle represent undefinedvalues which are shown by asterisk marks “*” on the lower left of theoutput line of the register 40 ₂ in FIG. 14.

Each of data stored sequentially into the register 234 ₄ to register 234₇ undergoes adding operations in the adding circuit 238 ₃ in everyoperation cycle out of eight operation cycles and is stored into theregister 40 ₃.

Data −g₀P₁₃+g₀P₉−g₃P₅−g₁P₁ is output from the adding circuit 238 ₃ in afirst operation cycle out of eight operation cycles, data−g₂P₁₃+g₀P₉−g₃P₅−g₁P₁+g₅P₁₃−g₇P₉+g₄P₅+g₆P₁ in a second operation cycleout of the eight operation cycles, data −g₁P₁₃+g₃P₉+g₀P₅+g₂P₁ in a thirdoperation cycle out of the eight operation cycles, data−g₁P₁₃+g₃P₉+g₀P₅+g₂P₁+g₆P₁₃−g₄P₉−g₇P₅−g₅P₁ in a fourth operation cycleout of the eight operation cycles, data g₀P₁₃+g₁P₉+g₂P₅+g₃P₁ in a fifthoperation cycle out of the eight operation cycles, datag₀P₁₃+g₁P₉+g₂P₅+g₃P₁−g₇P₁₃−g₆P₉−g₅P₅−g₄P₁ in a sixth operation cycle outof the eight operation cycles, data −g₃P₁₃+g₂P₉−g₁P₅+g₀P₁ in a seventhoperation cycle out of the eight operation cycles and data−g₃P₁₃+g₂P₉−g₁P₅+g₀P₁+g₄P₁₃−g₅P₉+g₆P₅−g₇P₁ in an eighth operationcycles. Out of data output from the adding circuit 238 ₃ in everyoperation cycle out of the eight operation cycles, data output in thesecond operation cycle, fourth operation cycle, sixth operation cycleand eighth operation cycle represent operation value F₃, operation valueF₅, operation value F₁ and operation value F₇ expressed in the equation(66) which are shown as F₃, F₅, F₁ and F₇ on a lower left of the outputline of the register 40 ₃ and data output in the first operation cycle,third operation cycle, fifth operation cycle and seventh operation cyclerepresent undefined values which are shown by asterisk marks “*” on thelower left of the output line of the register 40 ₃ in FIG. 14.

Each of data output from the MUX 224 ₉ and MUX 224 ₁₅, after havingundergone adding operations and subtracting operations in theadding/subtracting circuit 226 ₁ and having been stored in the register30 ₈ through the MUX 28 ₁ and having multiplexed by the fixedcoefficient P₇ in the P₁₄/P₇ fixed coefficient multiplying circuit 232₈, undergoes adding operations in the adding circuit 238 ₅ in everyoperation cycle out of the eight operation cycles and is stored in theregister 40 ₅.

Data (g₈+g₉) is output from the adding circuit 238 ₅ in a firstoperation cycle out of eight operation cycles, data (g₈+g₉+g₁₁+g₁₀) P₇in a second operation cycle out of the eight operation cycles, data(g₈+g₉+g₁₁+g₁₀+g₁₂+g₁₃) P₇ in a third operation cycle out of the eightoperation cycles, data (g₈+g₉+g₁₁+g₁₀+g₁₂+g₁₃+g₁₅+g₁₄) P₇ in a fourthoperation cycle out of the eight operation cycles, data (g₈−g₉) in afifth operation cycle out of the eight operation cycles, data(g₈−g₉+g₁₁−g₁₀) P₇ in a sixth operation cycle out of the eight operationcycles, data (g₈−g₉+g₁₁−g₁₀+g₁₂−g₁₃) P₇ in a seventh operation cycle outof the eight operation cycles and data (g₈−g₉+g₁₁−g₁₀+g₁₂−g₁₃+g₁₅−g₁₄)P₇ in an eighth operation cycles. Out of data output from the addingcircuit 238 ₅ in every operation cycle out of the eight operationcycles, data output in the fourth operation cycle and eighth operationcycle represent operation value F₈ and operation value F₁₂ expressed inthe equation (66) which are shown as F₈ and F₁₂ on a lower left of theoutput line of the register 40 ₅ and data output in the first operationcycle to third operation cycle and fifth operation cycle to seventhoperation cycle represent undefined values which are shown by asteriskmarks “*” on the lower left of the output line of the register 40 ₅ inFIG. 14.

Each of data stored sequentially into the register 234 ₉ to register 234₁₀ undergoes adding operations in the adding circuit 238 ₆ in everyoperation cycle out of eight operation cycles and is stored into theregister 40 ₆.

Data g₈P₁₁+g₉P₃ is output from the adding circuit 238 ₆ in a firstoperation cycle out of eight operation cycles, datag₈P₁₁+g₉P₃+g₁₅P₁₁−g₁₀P₃ in a second operation cycle out of the eightoperation cycles, data g₈P₁₁+g₉P₃+g₁₅P₁₁−g₁₀P₃−g₁₁P₁₁−g₁₃P₃ in a thirdoperation cycle out of the eight operation cycles, datag₈P₁₁+g₉P₃+g₁₅P₁₁−g₁₀P₃−g₁₁P₁₁−g₁₃P₃−g₁₂P₁₁+g₁₄P₃ in a fourth operationcycle out of the eight operation cycles, data −g₈P₁₁+g₉P₃ in a fifthoperation cycle out of the eight operation cycles, data−g₉P₁₁+g₈P₃+g₁₀P₁₁+g₁₁P₃ in a sixth operation cycle out of the eightoperation cycles, data −g₉P₁₁+g₈P₃+g₁₀P₁₁+g₁₁P₃+g₁₃P₁₁+g₁₂P₃ in aseventh operation cycle out of the eight operation cycles and data−g₉P₁₁+g₈P₃+g₁₀P₁₁+g₁₁P₃+g₁₃P₁₁+g₁₂P₃−g₁₄P₁₁+g₁₅P₃ in an eighthoperation cycle. Out of data output from the adding circuit 238 ₆ inevery operation cycle out of the eight operation cycles, data output inthe fourth operation cycle and eighth operation cycle representoperation value F₁₀ and operation value F₁₄ expressed in the equation(66) which are shown as F₁₀ and F₁₄ on a lower left of the output lineof the register 40 ₃ and data output in the first operation cycle tothird operation cycle and fifth operation cycle to seventh operationcycle represent undefined values which are shown by asterisk marks “*”on the lower left of the output line of the register 40 ₃ in FIG. 14.Each of data output from the MUX 224 ₁₂, MUX 224 ₁₃, MUX 224 ₁₄ and MUX224 ₁₆ is stored into the register 30 ₁₁, register 30 ₁₂, register 30 ₁₃and register 30 ₁₅ and then is multiplied by each of fixed coefficientP₁₃, fixed coefficient P₉, fixed coefficient P₅ and fixed coefficient P₁in each of the corresponding P₈/P₁₃ fixed coefficient multiplyingcircuits 232 ₁₁, P₆/P₉ fixed coefficient multiplying circuit 232 ₁₂,P₄/P₅ fixed coefficient multiplying circuit 232 ₁₃ and P₀/P₁ fixedcoefficient multiplying circuit 232 ₁₅. Each of the resulting data isstored in the register 234 ₁₁ to register 234 ₁₅ undergoes addingoperations in every operation cycle out of the eight operation cyclesand then is stored in the register 40 ₄.

Data g₈P₁₃+g₉P₉+g₁₀P₅+g₁₁P₁ is output from the adding circuit 238 ₄ in afirst operation cycle out of eight operation cycles, datag₈P₁₃+g₉P₉+g₁₀P₅+g₁₁P₁−g₁₅P₁₃−g₁₄P₉−g₁₃P₅−g₁₂P₁ in a second operationcycle out of the eight operation cycles, data −g₁₀P₁₃+g₈P₉−g₁₁P₅−g₉P₁ ina third operation cycle out of the eight operation cycles, data−g₁₀P₁₃+g₈P₉−g₁₁P₅−g₉P₁+g₁₃P₁₃−g₁₅P₉+g₁₂P₅+g₁₄P₁ in a fourth operationcycle out of the eight operation cycles, data −g₉P₁₃+g₁₁P₉+g₈P₃+g₁₀P₁ ina fifth operation cycle out of the eight operation cycles, data−g₉P₁₃+g₁₁P₉+g₈P₅+g₁₀P₁+g₁₄P₁₃−g₁₂P₉−g₁₅P₅−g₁₃P₁ in a sixth operationcycle out of the eight operation cycles, data −g₁₁P₁₃+g₁₀P₉−g₉P₅+g₈P₁ ina seventh operation cycle out of the eight operation cycles and data−g₁₁P₁₃+g₁₀P₉−g₉P₅+g₈P₁+g₁₂P₁₂−g₁₃P₉+g₁₄P₅−g₁₅P₁ in an eighth operationcycle. Out of data output from the adding circuit 238 ₄ in everyoperation cycle out of the eight operation cycles, data output in thesecond operation cycle, fourth operation cycle, sixth operation cycleand eighth operation cycle represent operation values F₁₁, F₁₃ and F₁₅expressed in the equation (66) which are shown as F₁₁, F₁₃ and F₁₅ on alower right of the output line of the register 40 ₄ and data output inthe first operation cycle, third operation cycle, fifth operation cycleand seventh operation cycle represent undefined values which are shownby asterisk marks “*” on the lower left of the output line of theregister 40 ₄ in FIG. 14.

By completing the above arithmetic operations, the primary 2-8-16 DCT onsixteen pieces of data contained in one line constituting the blockcomposed of 16×16 pieces of data is terminated. The same primary 2-8-16DCT as described above is performed on each of lines subsequent to anext line constituting the 16×16 data block and thereafter, and theprimary 2-8-6 DCT on all eight lines constituting the 8×8 data block isterminated in the similar manner. After the completion of the primary2-8-16 DCT on the all sixteen lines, a secondary 2-8-16 DCT is performedon each string of sixteen data strings constituting the 16×16 datablock. The transformation coefficient data obtained by completing thesecondary 2-8-16 DCT is used for compression of input 16×16 picturedata. Thus, transmission of compressed picture element data is madepossible by using the transformation coefficient data obtained byperforming the primary 2-8-16 DCT and secondary 2-8-16 DCT on the 16×16picture element data within an image to be transmitted for compressionof the 16×16 picture element data block.

Thus, according to the third embodiment, since the 16-16 DCT/2-8-16 DCTdevice is so configured that a part of the fixed coefficient multiplyingcircuit used in the 16-16 DCT is also used as the fixed coefficientmultiplying circuit required in the 2-8-16 DCT device, a high-speedcalculating characteristic obtained through the pipeline processing typearithmetic operation in the 16-16 DCT device can be fully maintainedeven in a miniaturized scale of the entire device for 16-16 DCT devicesand for the 2-8-16 DCT devices.

Fourth Embodiment

FIG. 15 is a schematic block diagram partially showing electricalconfigurations of a 16-16/2-8-16 IDCT device according to a fourthembodiment of the present invention. FIG. 16 is a schematic blockdiagram partially showing electrical configurations of the 16-16/2-8-16IDCT device according to the fourth embodiment. By overlaying a lineIV—IV in FIG. 15 on a line IV—IV in FIG. 16, overall configurations ofthe 16-16/2-8-16 IDCT device of the embodiment can be shown.Configurations of the fourth embodiment differ greatly from those in thethird embodiment in that the 16-16/2-8-16 IDCT, to obtain the originalimage data from the image data which is compressed in the 16-16/2-8-16DCT by performing the 16-16/2-8-16 DCT on the input data in the thirdembodiment, is performed on the compressed image data.

The 16-16 IDCT/2-8-16 IDCT of the embodiment, in the case of the 16-16IDCT, performs arithmetic operations according to a determinant equation(69) obtained by decompressing and rearranging the equation (18) and, inthe case of the 2-8-16 DCT, performs arithmetic operations according toa determinant equation (70) obtained by decompressing and rearrangingthe equation (22). The value h₀ to value h₁₅ in the determinant equation(69) are given by the equation (71) and the value g₀ to value g₁₅ in thedeterminant equation (70) are given by the equation (72).$\begin{matrix}\left. \begin{matrix}{{\frac{1}{2}\begin{bmatrix}{f_{0} + f_{8}} \\{f_{1} + f_{9}} \\{f_{2} + f_{10}} \\{f_{3} + f_{11}} \\{f_{4} + f_{12}} \\{f_{5} + f_{13}} \\{f_{6} + f_{14}} \\{f_{7} + f_{15}}\end{bmatrix}} = {\begin{bmatrix}{h_{0} + h_{8}} & h_{4} & h_{12} & h_{2} & h_{6} & h_{10} & h_{14} \\{h_{0} - h_{8}} & {- h_{12}} & h_{4} & {- h_{10}} & h_{2} & {- h_{14}} & {- h_{6}} \\{h_{0} - h_{8}} & h_{12} & {- h_{4}} & {- h_{6}} & h_{14} & {- h_{2}} & h_{10} \\{h_{0} + h_{8}} & {- h_{14}} & {- h_{12}} & h_{14} & h_{10} & {- h_{6}} & h_{2} \\{h_{0} + h_{8}} & {- h_{4}} & {- h_{12}} & h_{14} & {- h_{10}} & h_{6} & {- h_{2}} \\{h_{0} - h_{8}} & h_{12} & {- h_{4}} & h_{6} & {- h_{14}} & {- h_{2}} & {- h_{10}} \\{h_{0} - h_{8}} & {- h_{12}} & h_{4} & h_{10} & h_{2} & h_{14} & h_{6} \\{h_{0} + h_{8}} & h_{4} & {- h_{12}} & {- h_{2}} & {- h_{6}} & h_{10} & h_{14}\end{bmatrix}\begin{bmatrix}P_{7} \\P_{11} \\P_{3} \\P_{13} \\P_{9} \\P_{5} \\P_{1}\end{bmatrix}}} \\{{\frac{1}{2}\begin{bmatrix}{f_{0} - f_{8}} \\{f_{1} - f_{9}} \\{f_{2} - f_{10}} \\{f_{3} - f_{11}} \\{f_{4} - f_{12}} \\{f_{5} - f_{13}} \\{f_{6} - f_{14}} \\{f_{7} - f_{15}}\end{bmatrix}} = {\begin{bmatrix}h_{1} & h_{3} & h_{5} & h_{7} & h_{9} & h_{11} & {h_{13}h_{15}} \\{- h_{11}} & h_{1} & {- h_{9}} & h_{13} & h_{3} & {- h_{7}} & {{- h_{15}}h_{5}} \\h_{13} & {- h_{7}} & h_{1} & h_{5} & h_{11} & h_{15} & {h_{9}h_{3}} \\h_{9} & {- h_{5}} & {- h_{13}} & h_{1} & {- h_{15}} & {- h_{3}} & {h_{11}h_{7}} \\h_{7} & {- h_{11}} & {- h_{3}} & h_{15} & h_{1} & h_{13} & {{- h_{5}}h_{9}} \\{- h_{3}} & {- h_{9}} & {- h_{15}} & h_{11} & h_{5} & h_{1} & {{- h_{7}}h_{13}} \\h_{5} & h_{15} & {- h_{7}} & {- h_{3}} & {- h_{13}} & h_{9} & {h_{1}h_{11}} \\{- h_{15}} & h_{13} & {- h_{11}} & h_{9} & {- h_{7}} & h_{5} & {{- h_{3}}h_{1}}\end{bmatrix}\begin{bmatrix}P_{14} \\P_{12} \\P_{10} \\P_{8} \\P_{6} \\P_{4} \\P_{2} \\P_{0}\end{bmatrix}}}\end{matrix} \right\} & (69) \\\left. \begin{matrix}{\begin{bmatrix}f_{0} \\f_{2} \\f_{4} \\f_{6} \\f_{8} \\f_{10} \\f_{12} \\f_{14}\end{bmatrix} = {\begin{bmatrix}{i_{0} + i_{7}} & i_{2} & i_{5} & i_{1} & i_{3} & i_{4} & i_{6} \\{i_{0} - i_{7}} & {- i_{5}} & i_{2} & {- i_{4}} & i_{1} & {- i_{6}} & {- i_{3}} \\{i_{0} - i_{7}} & i_{5} & {- i_{2}} & {- i_{3}} & i_{6} & i_{1} & i_{4} \\{i_{0} + i_{7}} & {- i_{2}} & {- i_{5}} & {- i_{6}} & i_{4} & {- i_{3}} & i_{1} \\{i_{0} + i_{7}} & {- i_{2}} & {- i_{5}} & i_{6} & {- i_{4}} & i_{3} & {- i_{1}} \\{i_{0} - i_{7}} & i_{5} & {- i_{2}} & i_{3} & {- i_{6}} & {- i_{1}} & {- i_{4}} \\{i_{0} - i_{7}} & {- i_{5}} & i_{2} & i_{4} & {- i_{1}} & i_{6} & i_{3} \\{i_{0} + i_{7}} & i_{2} & {- i_{5}} & {- i_{1}} & {- i_{3}} & {- i_{4}} & {- i_{6}}\end{bmatrix}\begin{bmatrix}P_{7} \\P_{11} \\P_{3} \\P_{13} \\P_{9} \\P_{5} \\P_{1}\end{bmatrix}}} \\{\begin{bmatrix}f_{1} \\f_{3} \\f_{5} \\f_{7} \\f_{9} \\f_{11} \\f_{13} \\f_{15}\end{bmatrix} = {\begin{bmatrix}{i_{8} + i_{15}} & i_{10} & i_{13} & i_{9} & i_{11} & i_{12} & i_{14} \\{i_{8} - i_{15}} & {- i_{13}} & i_{10} & {- i_{12}} & i_{9} & {- i_{14}} & {- i_{11}} \\{i_{8} - i_{15}} & i_{13} & {- i_{10}} & {- i_{11}} & i_{14} & i_{9} & i_{12} \\{i_{8} + i_{15}} & {- i_{10}} & {- i_{13}} & {- i_{14}} & i_{12} & {- i_{11}} & i_{9} \\{i_{8} + i_{15}} & {- i_{10}} & {- i_{13}} & i_{14} & {- i_{12}} & i_{11} & {- i_{9}} \\{i_{8} - i_{15}} & i_{13} & {- i_{10}} & i_{11} & {- i_{14}} & {- i_{9}} & {- i_{12}} \\{i_{8} - i_{15}} & {- i_{13}} & i_{10} & i_{12} & {- i_{9}} & i_{14} & i_{11} \\{i_{8} + i_{15}} & i_{10} & i_{13} & {- i_{9}} & {- i_{11}} & {- i_{12}} & {- i_{14}}\end{bmatrix}\begin{bmatrix}P_{7} \\P_{11} \\P_{3} \\P_{13} \\P_{9} \\P_{5} \\P_{1}\end{bmatrix}}}\end{matrix} \right\} & (70) \\\left. \begin{matrix}{{h_{0} = F_{0}},\quad {h_{2} = F_{2}},\quad {h_{4} = F_{4}},\quad {h_{6} = F_{6}},} \\{{h_{8} = F_{8}},\quad {h_{10} = F_{10}},\quad {h_{12} = F_{12}},\quad {h_{14} = F_{14}},} \\{{h_{1} = F_{1}},\quad {h_{3} = F_{3}},\quad {h_{5} = F_{5}},\quad {h_{7} = F_{7}},} \\{{h_{9} = F_{9}},\quad {h_{11} = F_{11}},\quad {h_{13} = F_{13}},\quad {h_{15} = F_{15}}}\end{matrix} \right\} & (71) \\\left. \begin{matrix}{{i_{0} = {F_{0} + F_{8}}},\quad {i_{1} = {F_{1} + F_{9}}},\quad {i_{2} = {F_{2} + F_{10}}},\quad {i_{3} = {F_{3} + F_{11}}},} \\{{i_{4} = {F_{5} + F_{13}}},\quad {i_{5} = {F_{6} + F_{14}}},\quad {i_{6} = {F_{7} + F_{15}}},\quad {i_{7} = {F_{4} + F_{12}}},} \\{{i_{8} = {F_{0} - F_{8}}},\quad {i_{9} = {F_{1} - F_{9}}},\quad {i_{10} = {F_{2} - F_{10}}},\quad {i_{11} = {F_{3} - F_{11}}},} \\{{i_{12} = {F_{5} - F_{13}}},\quad {i_{13} = {F_{6} - F_{14}}},\quad {i_{14} = {F_{7} - F_{15}}},\quad {i_{15} = {F_{4} - F_{12}}},}\end{matrix} \right\} & (72)\end{matrix}$

Moreover, the P₀ to P₁₅ in the equation (69) and equation (70) are sameas the P₀ to P₁₅ in the equation (65) and equation (66).

The MUX 312, in the case of the 16-16 IDCT, selectively outputs sixteenpieces of data contained in each line for the primary IDCT out of 16×16transformation coefficient data (hereafter called “data”) on which the16-16 IDCT is performed or each data of sixteen pieces of data F₀ todata F₁₅ contained in each line constituting the 16×16 data obtainedthrough the primary IDCT to corresponding register 14 ₀ to register 14₁₅ and, in the case of the 2-8-16 IDCT, stores data F₀ out of thesixteen pieces of data F₀ to data F₁₅ into the register 14 ₁ containedin the first register group 313, data F₈ to the register 14 ₂, data F₁to the register 14 ₃, data F₉ to the register 14 ₄, data F₂ to theregister 14 ₅, data F₁₀ to the register 14 ₆, data F₃ to the register 14₇, data F₁₁ to the register 14 ₈, data F₅ to the register 14 ₉, data F₁₃to the register 14 ₁₀ data F₆ to the register 14 ₁₁, data F₁₄ to theregister 14 ₁₂, data F₇ to the register 14 ₁₃, data F₁₅ to the register14 ₁₄, data F₄ to the register 14 ₁₅ and data F₁₂ to the register 14 ₁₆.

Each of the MUXs 16 ₁ to 16 ₈, 16 ₉₂, 16 ₁₀₂, 16 ₁₁₂, 16 ₁₂₂, 16 ₁₃₂, 16₁₄₂, 16 ₁₅₂ and 16 ₁₆₂, in the case of the 16-16 IDCT, selects “0” dataand, in the case of 2-8-16 IDCT, selects each of the registers 14 ₂, 14₄, 14 ₆, 14 ₈, 14 ₁₀, 14 ₁₂, 14 ₁₄ and 14 ₁₆. Each of the MUXs 16 ₉₁, 16₁₀₁, 16 ₁₁₁, 16 ₁₂₁, 16 ₁₃₁, 16 ₁₄₁, 16 ₁₅₁ and 16 ₁₆₁, in the case ofthe 16-16 IDCT, selects each of the registers 14 ₃, 14 ₇, 14 ₉, 14 ₁₃,14 ₁₄, 14 ₈, 14 ₁₀ and 14 ₁₄ and, in the case of the 2-8-16 IDCT,selects each of the registers 14 ₁, 14 ₃, 14 ₅, 14 ₇, 14 ₉, 14 ₁₁, 14 ₁₃and 14 ₁₅.

The adding circuit 18 ₁ constituting a first adding circuit group 317adds data output from the register 14 ₁ to data output from the MUX 16₁, the adding circuit 18 ₂ adds data output from the register 14 ₃ todata output from the MUX 16 ₂, the adding circuit 18 ₃ adds data outputfrom the register 14 ₅ to data output from the MUX 16 ₃, the addingcircuit 18 ₄ adds data output from the register 14 ₇ to data output fromthe MUX 16 ₄, the adding circuit 18 ₅ adds A data output from theregister 14 ₉ to data output from the MUX 16 ₅, the adding circuit 18 ₆adds data output from the register 14 ₁₁ to data output from the MUX 16₆, the adding circuit 18 ₇ adds data output from the register 14 ₁₃ todata output from the MUX 16 ₇ and the adding circuit 18 ₈ adds dataoutput from the register 14 ₁₅ to data output from the MUX 16 ₈.

The subtracting circuit 20 ₁ constituting a subtracting circuit group319 performs subtracting operations on data output from the MUX 16 ₉₁and data output from the MUX 16 ₉₂, the subtracting circuit 20 ₂performs subtracting operations on data output from the MUX 16 ₁₀₁ anddata output from the MUX 16 ₁₀₂, the subtracting circuit 20 ₃ performssubtracting operations on data output from the MUX 16 ₁₁₁ and dataoutput from the MUX 16 ₁₁₂, the subtracting circuit 20 ₄ performssubtracting operations on data output from the MUX 16 ₁₂₁ and dataoutput from the MUX 16 ₁₂₂, the subtracting circuit 20 ₅ performssubtracting operations on data output from the MUX 16 ₁₃₁ and dataoutput from the MUX 16 ₁₃₂, the subtracting circuit 20 ₆ performssubtracting operations on data output from the MUX 16 ₁₄₁ and dataoutput from the MUX 16 ₁₄₂, the subtracting circuit 20 ₇ performssubtracting operations on data output from the MUX 16 ₁₅₁ and dataoutput from the MUX 16 ₁₅₂ and the subtracting circuit 20 ₈ performssubtracting operations on data output from the MUX 16 ₁₆₁ and dataoutput from the MUX 16 ₁₆₂.

Data output from each of the adding circuit 18 ₁ to adding circuit 18 ₈is stored into each of the corresponding register 22 ₁ to register 22 ₈contained in a second register group 321 and data output from each ofthe subtracting circuit 20 ₁ to subtracting circuit 20 ₈ is stored intoeach of the corresponding register 22 ₉ to register 22 ₁₆.

The MUX 324 ₁ constituting a second MUX group is connected to an outputof each of the register 22 ₁ to register 22 ₈ and, in the case of boththe 16-16 IDCT and2-8-16 IDCT, selects the register 22 ₁ eight times andsequentially outputs eight pieces of data. The MUX 324 ₂, in the case ofthe 16-16 IDCT, selects the register 22 ₅ eight times and sequentiallyoutputs eight pieces of data and, in the case of the 2-8-16 IDCT,selects the register 22 ₈ and sequentially outputs eight pieces of data.

The MUX 324 ₃, in the case of the 16-16 IDCT, selects the register inthe order of the registers 22 ₃, 22 ₇, 22 ₇, 22 ₃, 22 ₃, 22 ₇, 22 ₇ and22 ₃ and sequentially outputs eight pieces of data and, in the case ofthe 2-8-16 IDCT, selects the register in the order of the register 22 ₃,22 ₆, 22 ₆, 22 ₃, 22 ₃, 22 ₆, 22 ₆ and 22 ₃ and sequentially outputseight pieces of data.

The MUX 324 ₄, in the case of the 16-16 IDCT, selects the register inthe order of the registers 22 ₇, 22 ₃, 22 ₃, 22 ₇, 22 ₇, 22 ₃ 22 ₃ and22 ₇ and sequentially outputs eight pieces of data and, in the case ofthe 2-8-16 IDCT, selects the register in the order of the register 22 ₆,22 ₃, 22 ₃, 22 ₆, 22 ₆, 22 ₃, 22 ₃ and 22 ₃ and sequentially outputseight pieces of data.

The MUX 324 ₅, in the case of the 16-16 IDCT, selects the register inthe order of the registers 22 ₂, 22 ₆, 22 ₄, 22 ₈, 22 ₈, 22 ₄, 22 ₆ and22 ₂ and sequentially outputs eight pieces of data and, in the case ofthe 2-8-16 IDCT, selects the register in the order of the register 22 ₂,22 ₅, 22 ₄, 22 ₇, 22 ₇, 22 ₄, 22 ₅ and 22 ₂ and sequentially outputseight pieces of data.

The MUX 324 ₆, in the case of the 16-16 IDCT, selects the register inthe order of the registers 22 ₄, 22 ₂, 22 ₈, 22 ₆, 22 ₆, 22 ₈, 22 ₂ and22 ₄ and sequentially outputs eight pieces of data and, in the case ofthe 2-8-16 IDCT, selects the register in the order of the register 22 ₄,22 ₂, 22 ₇, 22 ₅, 22 ₅, 22 ₇, 22 ₂ and 22 ₄ and sequentially outputseight pieces of data.

The MUX 324 ₇, in the case of the 16-16 IDCT, selects the register inthe order of the registers 22 ₆, 22 ₈, 22 ₂, 22 ₄, 22 ₄, 22 ₂, 22 ₈ and22 ₆ and sequentially outputs eight pieces of data and, in the case ofthe 2-8-16 IDCT, selects the register in the order of the register 22 ₅,22 ₇, 22 ₂, 22 ₄, 22 ₄, 22 ₂, 22 ₇ and 22 ₅ and sequentially outputseight pieces of data.

The MUX 324 ₈, in the case of the 16-16 IDCT, selects the register inthe order of the registers 22 ₈, 22 ₄, 22 ₆, 22 ₂, 22 ₂, 22 ₆, 22 ₄ and22 ₈ and sequentially outputs eight pieces of data and, in the case ofthe 2-8-16 IDCT, selects the register in the order of the register 22 ₇,22 ₄, 22 ₅, 22 ₂, 22 ₂, 22 ₅, 22 ₄ and 22 ₇ and sequentially outputseight pieces of data.

The MUX 324 ₉, in the case of the 16-16 IDCT, selects the register inthe order of the registers 22₉, 22 ₁₄, 22 ₁₅, 22 ₁₃, 22 ₁₂, 22 ₁₀, 22 ₁₁and 22 ₁₆ and sequentially outputs eight pieces of data and, in the caseof the 2-8-16 IDCT, selects the register 22 ₁₆ eight times repeatedlyand sequentially outputs eight pieces of data.

The MUX 324 ₁₀, in the case of the 16-16 IDCT, selects the register inthe order of the registers 22 ₁₀, 22 ₉, 22 ₁₂, 22 ₁₁, 22 ₁₄, 22 ₁₃, 22₁₆ and 22 ₁₅ and sequentially outputs eight pieces of data and, in thecase of the 2-8-16 IDCT, selects the register in the order of theregister 22 ₁₁, 22 ₁₄, 22 ₁₄, 22 ₁₁, 22 ₁₁, 22 ₁₄, 22 ₁₄ and 22 ₁₁ andsequentially outputs eight pieces of data.

The MUX 324 ₁₁, in the case of the 16-16 IDCT, selects the register inthe order of the registers 22 ₁₁, 22 ₁₃, 22 ₉, 22 ₁₅, 22 ₁₀, 22 ₁₆, 22₁₂ and 22 ₁₄ and sequentially outputs eight pieces of data and, in thecase of the 2-8-16 IDCT, selects the register in the order of theregister 22 ₁₄, 22 ₁₁, 22 ₁₁, 22 ₁₄, 22 ₁₄, 22 ₁₁, 22 ₁₁ and 22 ₁₄ andsequentially outputs eight pieces of data.

The MUX 324 ₁₂, in the case of the 16-16 IDCT, selects the register inthe order of the registers 22 ₁₂, 22 ₁₅, 22 ₁₁, 22 ₉, 22 ₁₆, 22 ₁₄, 22₁₀ and 22 ₁₃ and sequentially outputs eight pieces of data and, in thecase of the 2-8-16 IDCT, selects the register in the order of theregister 22 ₁₀, 22 ₁₃, 22 ₁₂, 22 ₁₅, 22 ₁₅, 22 ₁₂, 22 ₁₃ and 22 ₁₀ andsequentially outputs eight pieces of data.

The MUX 324 ₁₃, in the case of the 16-16 IDCT, selects the register inthe order of the registers 22 ₁₃, 22 ₁₀, 22 ₁₄, 22 ₁₆, 22 ₉, 22 ₁₁, 22₁₅ and 22 ₁₂ and sequentially outputs eight pieces of data and, in thecase of the 2-8-16 IDCT, selects the register in the order of theregister 22 ₁₂, 22 ₁₀, 22 ₁₅, 22 ₁₃, 22 ₁₃, 22 ₁₅, 22 ₁₀ and 22 ₁₂ andsequentially outputs eight pieces of data.

The MUX 324 ₁₄, in the case of the 16-16 IDCT, selects the register inthe order of the registers 22 ₁₄, 22 ₁₂, 22 ₁₆, 22 ₁₀, 22 ₁₅, 22 ₉, 22₁₃ and 22 ₁₁ and sequentially outputs eight pieces of data and, in thecase of the 2-8-16 IDCT, selects the register in the order of theregister 22 ₁₃, 22 ₁₅, 22 ₁₀, 22 ₁₂, 22 ₁₂, 22 ₁₀, 22 ₁₅ and 22 ₁₃ andsequentially outputs eight pieces of data.

The MUX 324 ₁₅, in the case of the 16-16 IDCT, selects the register inthe order of the registers 22 ₁₅, 22 ₁₆, 22 ₁₃, 22 ₁₄, 22 ₁₁, 22 ₁₂, 22₉ and 22 ₁₀ and sequentially outputs eight pieces of data and, in thecase of the 2-8-16 IDCT, selects the register in the order of theregister 22 ₁₅, 22 ₁₂, 22 ₁₃, 22 ₁₀, 22 ₁₀, 22 ₁₃, 22 ₁₂ and 22 ₁₅ andsequentially outputs eight pieces of data.

The MUX 324 ₁₆, in the case of the 16-16 IDCT, selects the register inthe order of the registers 22 ₁₆, 22 ₁₁, 22 ₁₀, 22 ₁₂, 22 ₁₃, 22 ₁₅, 22₁₄ and 22 ₉ and sequentially outputs eight pieces of data and, in thecase of the 2-8-16 IDCT, selects the register 22 ₁₆ eight timesrepeatedly and sequentially outputs eight pieces of data.

The adding/subtracting circuit 326 ₁ constituting the firstadding/subtracting circuit group 325 performs adding operations on eightpieces of data output sequentially from the MUX 324 ₁ in a first order,fourth order, fifth order and eighth order and on eight pieces of dataoutput sequentially from the MUX 324 ₂ in the first order, fourth order,fifth order and eighth order and performs subtracting operations oneight pieces of data output sequentially from the MUX 324 ₁ in a secondorder, third order, sixth order and seventh order and on eight pieces ofdata output sequentially from the MUX 324 ₂ in the second order, thirdorder, sixth order and seventh order. In the subtracting operations bythe adding/subtracting circuit 326 ₁, data output from the MUX 324 ₂ issubtracted from data output from the MUX 324 ₁.

The adding/subtracting circuit 326 ₂ constituting the firstadding/subtracting circuit group 325 performs adding operations on eightpieces of data output sequentially from the MUX 324 ₉ in a first order,fourth order, fifth order and eighth order and on eight pieces of dataoutput sequentially from the MUX 324 ₁₆ in the first order, fourthorder, fifth order and eighth order and performs subtracting operationson eight pieces of data output sequentially from the MUX 324 ₁ in asecond order, third order, sixth order and seventh order and on eightpieces of data output sequentially from the MUX 324 ₂ in the secondorder, third order, sixth order and seventh order. In the subtractingoperations by the adding/subtracting circuit 326 ₂, data output from theMUX 324 ₁₆ is subtracted from data output from the MUX 324 ₉.

The MUX 28 ₁ constituting the second MUX group 327, in the case of the16-16 IDCT, selects sequentially eight pieces of data output from theMUX 324 ₉ and, in the 2-8-16 IDCT, selects sequentially eight pieces ofdata output from the adding/subtracting circuit 326 ₂. The MUX 28 ₂, inthe case of the 16-16 IDCT, sequentially selects eight pieces of dataoutput from the MUX 324 ₁₅ and, in the case of the 2-8-16 IDCT, selects“0” data eight times and outputs them. The MUX 28 ₃, in the case of the16-16 IDCT, selects sequentially eight pieces of data output from theMUX 324 ₁₆ and outputs them and, in the case of the 2-8-16 IDCT, selectssequentially eight pieces of data output from the adding/subtractingcircuit 324 ₁₅ and sequentially outputs them.

The register 30 ₁ constituting a second register group 329 storessequentially eight pieces of operation results output in order from theadding/subtracting circuit 326 ₁. The register 30 ₂ stores eight piecesof data selected sequentially and output from the MUX 324 ₃. Theregister 30 ₃ stores eight pieces of data selected sequentially andoutput from the MUX 324 ₄. The register 30 ₄ stores eight pieces of dataselected sequentially and output from the MUX 324 ₅. The register 30 ₅stores eight pieces of data selected sequentially and output from theMUX 324 ₆. The register 30 ₆ stores eight pieces of data selectedsequentially and output from the MUX 324 ₇. The register 30 ₇ storeseight pieces of data selected sequentially and output from the MUX 324₈.

The register 30 ₈ stores eight pieces of data selected sequentially andoutput from the MUX 28 ₁. The register 30 ₉ stores eight pieces of dataselected sequentially and output from the MUX 324 ₁₀. The register 30 ₁₀stores eight pieces of data selected sequentially and output from theMUX 324 ₁₁. The register 30 ₁₁ stores eight pieces of data selectedsequentially and output from the MUX 324 ₁₂. The register 30 ₁₂ storeseight pieces of data selected sequentially and output from the MUX 324₁₃. The register 30 ₁₃ stores eight pieces of data selected sequentiallyand output from the MUX 324 ₁₄. The register 30 ₁₄ stores eight piecesof data selected sequentially and output from the MUX 28 ₂. The register30 ₁₅ stores eight pieces of data selected sequentially and output fromthe MUX 283.

The P₇ coefficient multiplying circuit 232 ₁ multiplies each of eightpieces of data output from the register 30 ₁ by a fixed coefficient P₇.The P₁₁ coefficient multiplying circuit 232 ₂ multiplies each of eightpieces of data output from the register 30 ₂ by a fixed coefficient P₁₁.The P₃ coefficient multiplying circuit 232 ₃ multiplies each of eightpieces of data output from the register 30 ₃ by a fixed coefficient P₃.The P₁₃ coefficient multiplying circuit 232 ₄ multiplies each of eightpieces of data output from the register 30 ₄ by a fixed coefficient P₁₃.The P₉ coefficient multiplying circuit 232 ₅ multiplies each of eightpieces of data output from the register 30 ₅ by a fixed coefficient P₉.The P₅ coefficient multiplying circuit 232 ₆ multiplies each of eightpieces of data output from the register 30 ₆ by a fixed coefficient P₅.The P₁ coefficient multiplying circuit 232 ₇ multiplies each of eightpieces of data output from the register 30 ₇ by a fixed coefficient P₁.

The P₁₄/P₇ coefficient multiplying circuit 232 ₈, in the case of the16-16 DCT, multiplies each of eight pieces of data output sequentiallyfrom the register 30 ₈ by a fixed coefficient P₁₄ and, in the case ofthe 2-8-16 DCT, multiplies each of the eight pieces of data outputsequentially from the register 30 ₈ by a fixed coefficient P₇. TheP₁₂/P₁₁ coefficient multiplying circuit 232 ₉, in the case of the 16-16DCT, multiplies each of eight pieces of data output sequentially fromthe register 30 ₉ by a fixed coefficient P₁₂ and, in the case of the2-8-16 DCT, multiplies each of the eight pieces of data outputsequentially from the register 30 ₉ by a fixed coefficient P₁₁. TheP₁₀/P₃ coefficient multiplying circuit 232 ₁₀, in the case of the 16-16DCT, multiplies each of eight pieces of data output sequentially fromthe register 30 ₁₀ by a fixed coefficient P₁₀ and, in the case of the2-8-16 DCT, multiplies each of the eight pieces of data outputsequentially from the register 30 ₁₀ by a fixed coefficient P₃. TheP₈/P₁₃ coefficient multiplying circuit 232 ₁₁, in the case of the 16-16DCT, multiplies each of eight pieces of data output sequentially fromthe register 30 ₁₁ by a fixed coefficient P₈ and, in the case of the2-8-16 DCT, multiplies each of the eight pieces of data outputsequentially from the register 30 ₁₁ by a fixed coefficient P₁₃.

The P₆/P₉ coefficient multiplying circuit 232 ₁₂, in the case of the16-16 DCT, multiplies each of eight pieces of data output sequentiallyfrom the register 30 ₁₂ by a fixed coefficient P₆ and, in the case ofthe 2-8-16 DCT, multiplies each of the eight pieces of data outputsequentially from the register 30 ₁₂ by a fixed coefficient P₉. TheP₄/P₅ coefficient multiplying circuit 232 ₁₃, in the case of the 16-16DCT, multiplies each of eight pieces of data output sequentially fromthe register 30 ₁₃ by a fixed coefficient P₄ and, in the case of the2-8-16 DCT, multiplies each of the eight pieces of data outputsequentially from the register 30 ₁₃ by a fixed coefficient P₅.

The P₂ coefficient multiplying circuit 232 ₁₄, in the case of the 16-16DCT, multiplies each of eight pieces of data output sequentially fromthe register 30 ₁₄ by a fixed coefficient P₂. The P₀/P₁ coefficientmultiplying circuit 232 ₁₅, in the case of the 16-16 DCT, multiplieseach of eight pieces of data output sequentially from the register 30 ₁₅by a fixed coefficient P₀ and, in the case of the 2-8-16 DCT, multiplieseach of the eight pieces of data output sequentially from the register30 ₁₅ by a fixed coefficient P₁.

The register 334 ₁ constituting a fourth register group 333, in the caseof both the 16-16 IDCT and the 2-8-16 IDCT, sequentially stores each ofeight pieces of data output, in order, from the P₇ coefficientmultiplying circuit 232 ₁ and outputs data to be output sequentially ina first order to eighth order as positive values. The register 334 ₂, inthe case of both the 16-16 IDCT and the 2-8-16 IDCT, sequentially storeseach of eight pieces of data output, in order, from the P₁₁ coefficientmultiplying circuit 232 ₂ and outputs data to be output sequentially ina first order, third order, sixth order and eighth order as positivevalues and outputs data to be output sequentially in a second order,fourth order, fifth order and seventh order as negative values. Theregister 334 ₃, in the case of both the 16-16 IDCT and the 2-8-16 IDCT,sequentially stores each of eight pieces of data output, in order, fromthe P₃ coefficient multiplying circuit 232 ₃ and outputs data to beoutput sequentially in a first order, second order and seventh order aspositive values and outputs data to be output sequentially in a thirdorder to sixth order and eighth order as negative values.

The register 334 ₄ stores each of eight pieces of data outputsequentially from the P₁₃ coefficient multiplying circuit 232 ₄ and, inthe case of the 16-16 IDCT, outputs data to be output in a first order,fourth order to seventh order as positive values and outputs data to beoutput in a second order, third order and eighth order as negativevalues, and in the case of the 2-8-16 IDCT, outputs data to be output inthe first order, fifth order to seventh order as positive values andoutputs data to be output in the second order to fourth order and eighthorder as negative values. The register 334 ₅ stores each of eight piecesof data output sequentially from the P₉ coefficient multiplying circuit232 ₅ and, in the case of the 16-16 IDCT, outputs data to be output in afirst order to fourth order and seventh order as positive values andoutputs data to be output in a fifth order, sixth order and eighth orderas negative values, and in the case of the 2-8-16 IDCT, outputs data tobe output in the first order to fourth order as positive values andoutputs data to be output in the fifth order to eighth order as negativevalues. The register 334 ₆ stores each of eight pieces of data outputsequentially from the P₅ coefficient multiplying circuit 232 ₆ and, inthe case of the 16-16 IDCT, outputs data to be output in a first order,fifth order, seventh order and eighth order as positive values andoutputs data to be output in a second order to fourth order and sixthorder as negative values, and in the case of the 2-8-16 IDCT, outputsdata to be output in the first order, third order, fifth order andseventh order as positive values and outputs data to be output in thesecond order, fourth order, sixth order and eighth order as negativevalues. The register 334 ₇ stores each of eight pieces of data outputsequentially from the P₁ coefficient multiplying circuit 232 ₇ and, inthe case of the 16-16 IDCT, outputs data to be output in a first order,third order, fourth order, seventh order and eighth order as positivevalues and outputs data to be output in a second order, fifth order andsixth order as negative values, and in the case of the 2-8-16 IDCT,outputs data to be output in the first order, third order, fourth orderand seventh order as positive values and outputs data to be output inthe second order, fifth order, sixth order and eighth order as negativevalues. The register 334 ₈ stores each of eight pieces of data outputsequentially from the P₁₄/P₇ coefficient multiplying circuit 232 ₈ and,in the case of the 16-16 IDCT, outputs data to be output in a firstorder, third order to fifth order and seventh order as positive valuesand outputs data to be output in a second order, sixth order and eighthorder as negative values, and in the case of the 2-8-16 IDCT, outputsdata to be output in the first order to eighth order as positive values.The register 334 ₉ stores each of eight pieces of data outputsequentially from the P₁₂/P₁₁ coefficient multiplying circuit 232 ₉ and,in the case of the 16-16 IDCT, outputs data to be output in a firstorder, second order, seventh order and eighth order as positive valuesand outputs data to be output in a second order to sixth order asnegative values, and in the case of the 2-8-16 IDCT, outputs data to beoutput in the first order, third order, sixth order and eighth order aspositive values and outputs data to be output in the second order,fourth order, fifth order and seventh order as negative values. Theregister 334 ₁₀ stores each of eight pieces of data output sequentiallyfrom the P₁₀/P₃ coefficient multiplying circuit 232 ₁₀ and, in the caseof the 16-16 IDCT, outputs data to be output in a first order and thirdorder as positive values and outputs data to be output in a secondorder, fourth order to eighth order as negative values, and in the caseof the 2-8-16 IDCT, outputs data to be output in the first order, secondorder, seventh order and eighth order as positive values and outputsdata to be output in the third order to sixth order as negative values.The register 334 ₁₁ stores each of eight pieces of data outputsequentially from the P₈/P₁₃ coefficient multiplying circuit 232 ₁₁ and,in the case of the 16-16 IDCT, outputs data to be output in a firstorder, fourth order to sixth order and eighth order as positive valuesand outputs data to be output in a second order, third order and seventhorder as negative values, and in the case of the 2-8-16 IDCT, outputsdata to be output in the first order, fifth order to seventh order aspositive values and outputs data to be output in the second to fourthorder and eighth order as negative values. The register 334 ₁₂ storeseach of eight pieces of data output sequentially from the P₆/P₉coefficient multiplying circuit 232 ₁₂ and, in the case of the 16-16IDCT, outputs data to be output in a first order to third order, fifthorder and sixth order as positive values and outputs data to be outputin a fourth order, seventh order and eighth order as negative values,and in the case of the 2-8-16 IDCT, outputs data to be output in thefirst order to fourth order as positive values and outputs data to beoutput in the fifth order to eighth order as negative values. Theregister 334 ₁₃ stores each of eight pieces of data output sequentiallyfrom the P₄/P₅ coefficient multiplying circuit 232 ₁₃ and, in the caseof the 16-16 IDCT, outputs data to be output in a first order, thirdorder, fifth order to eighth order as positive values and outputs datato be output in a second order and fourth order as negative values, andin the case of the 2-8-16 IDCT, outputs data to be output in the firstorder, third order, fifth order and seventh order as positive values andoutputs data to be output in the second order, fourth order, sixth orderand eighth order as negative values. The register 334 ₁₄ stores each ofeight pieces of data output sequentially from the P2 coefficientmultiplying circuit 232 ₁₄ and, in the case of both the 16-16 IDCT andthe 2-8-16 IDCT, outputs data to be output in the first order, fourthorder, sixth order and seventh order as positive values and outputs dataoutput in a second order, third order, fifth order and eighth order asnegative values. The register 334 ₁₅ stores each of eight pieces of dataoutput sequentially from the P₀/P₁ coefficient multiplying circuit 232₁₅ and, in the case of the 16-16 IDCT, outputs data to be output in afirst order to fourth order and sixth order to eighth order as positivevalues and outputs data to be output in a fifth order as negativevalues, and in the case of the 2-8-16 IDCT, outputs data to be output inthe first order, third order, fourth order and seventh order as positivevalues and outputs data to be output in the second order, fifth order,sixth order and eighth order as negative values.

The adding circuit 338 ₃, in the case of both the 16-16 IDCT and 2-8-16IDCT, performs adding operations on eight pieces of data outputsequentially from the register 334 ₁ to register 334 ₇. The register 40₃ stores data output from the adding circuit 338 ₃.

The adding circuit 338 ₄, in the case of both the 16-16 IDCT and 2-8-16IDCT, performs adding operations on eight pieces of data outputsequentially from the register 334 ₈ to register 334 ₁₅. The register 40₄ stores data output from the adding circuit 36 ₄.

Data from the register 40 ₃ is fed to a summand input of the addingcircuit 44 and a minuend input of the subtracting circuit 42 and datafrom the register 40 ₄ is fed to a summand input of the adding circuit44 and to a minuend input of the subtracting circuit 42. Data outputfrom the subtracting circuit 42 is fed to the register 46 contained inthe sixth register group 45 and data output from the adding circuit 44is fed to the register 48 contained in the sixth register group 45.Other configurations of the fourth embodiment are same as those in thethird embodiment and same reference numbers as given to FIG. 13 and FIG.14 are assigned to components shown in FIG. 15 and FIG. 16, and relateddescriptions are omitted.

Operations in the fourth embodiment will be described by referring toFIG. 15 and FIG. 16. First, the operations for the 16-16 DCT will beexplained.

Each of sixteen pieces of picture element data f₀ to picture elementdata f₁₅ for each string constituting the 16×16 transformationcoefficient data transmitted after being compressed by performing the16-16 DCT on the 16×16 picture elements sequentially from the MUX 312,is stored into each of register 14 ₁ to register 14 ₁₆ constituting thefirst register group 313 which corresponds to each of sixteen pieces ofdata F₀ to data F₁₅.

Since the MUXs 16 ₁ to 16 ₈, 16 ₉₂, 16 ₁₀₂, 16 ₁₁₂, 16 ₁₂₂, 16 ₁₃₂, 16₁₄₂, 16 ₁₅₂, 16 ₁₆₂ have selected “0” data respectively, and the MUXs16₉₁, 16 ₁₀₁, 16 ₁₁₁, 16 ₁₂₁, 16 ₁₃₁, 16 ₁₄₁, 16 ₁₅₁ and 16 ₁₆₁ haveselected the registers 14 ₃, 14 ₇, 14 ₉, 14 ₁₃, 14 ₄, 14 ₁₀ and 14 ₁₄,respectively, data F₀=h₀ is output from the adding circuit 18 ₁, dataF₂=h₂ from the adding circuit 18 ₂, data F₄=h₄ from the adding circuit18 ₃, data F₆=h₆ from the adding circuit 18 ₄, data F₈=h₈ from theadding circuit 18 ₅, data F₁₀=h₁ from the adding circuit 18 ₅, dataF₁₀=h₁₀ from the adding circuit 18 ₆, data F₁₂=h₁₂ from the addingcircuit 18 ₇, data F₁₄=h₁₄ from the adding circuit 18 ₈, data F₁=h₁ fromthe subtracting circuit 20 ₁, data F₃=h₃ from the subtracting circuit 20₂, data F₅=h₅ from the subtracting circuit 20 ₃, data F₇=h₇ from thesubtracting circuit 20 ₄, data F₉=h₉ from the subtracting circuit 20 ₅,data F₁₁=h₁₁ from the subtracting circuit 20 ₆, data F₁₃=h₁₃ from thesubtracting circuit 20 ₇ and data F₁₅=h₁₅ from the subtracting circuit20 ₈.

Data h₀ output from the adding circuit 18 ₁ is stored into the register22 ₁, data h₂ output from the adding circuit 18 ₂ is stored into theregister 22 ₂, data h₄ output from the adding circuit 18 ₃ is storedinto the register 22 ₃, data h₆ output from the adding circuit 18 ₄ isstored into the register 22 ₄, data h₈ output from the adding circuit 18₅ is stored into the register 22 ₅, data h₁₀ output from the addingcircuit 18 ₆, data h₁₂ output from the register 22 ₆is stored into theadding circuit 18 ₇ and h₁₄ output from the register 22 ₇ is stored intothe adding circuit 18 ₈.

Data h₁ output from the subtracting circuit 20 ₁ is stored into theregister 22 ₉, data h₃ output from the subtracting circuit 20 ₂ isstored into the register 22 ₁₀, data h₅ output from the subtractingcircuit 20 ₃ is stored into the register 22 ₁₁, data h₇ output from thesubtracting circuit 20 ₄ is stored into the register 22 ₁₂, data h₉output from the subtracting circuit 20 ₆ is stored into the register 22₁₃, data h₁₁ output from the subtracting circuit 20 ₇ is stored into theregister 22 ₁₅ and data h₁₅ output from the subtracting circuit 20 ₈ isstored into the register 22 ₁₆.

Data h₀ output from the register 22 ₁ is selected by the MUX 324 ₁ inevery operation cycle out of eight operation cycles and is fed to theadding/subtracting circuit 326 ₁, and data h₈ output from the register22 ₅ is selected by the MUX 324 ₂ in every operation cycle out of eightoperation cycles and is fed to the adding/subtracting circuit 326 ₁ andthen each of data h₀+h₈, data h₀−h₈, data h₀−h₈, data h₀+h₈, data h₀+h₈,data h₀−h₈, data h₀−h₈ and data h₀+h₈ is output from theadding/subtracting circuit 326 ₁ sequentially in every operation cycleout of eight operation cycles and is stored into the register 30 ₁. Datah₀, h₂, h₄, h₆, h₈, h₁₀, h₁₂ and h₁₄ output from the register 22 ₁ toregister 22 ₈ in every operation cycle out of eight operation cycles isselected by the MUX 324 ₃ in every operation cycle out of the eightoperation cycles and each of data h₄, h₁₂, h₁₂, h₄, h₄, h₁₂, h₁₂ and h₄is output sequentially from the MUX 324 ₃ and stored into the register30 ₂. Data h₀, h₂, h₄, h₆, h₈, h₁₀, h₁₂ and h₁₄ output from the register22 ₁ to register 22 ₈ in every operation cycle out of eight operationcycles is selected by the MUX 324 ₄ in every operation cycle out of theeight operation cycles and each of data h₁₂, h₄, h₄, h₁₂, h₁₂, h₄, h₄and h₁₂ is output sequentially from the MUX 324 ₄ and stored into theregister 30 ₃. Data h₀, h₂, h₄, h₆, h₈, h₁₀, h₁₂ and h₁₄ output from theregister 22 ₁ to register 22 ₈ in every operation cycle out of eightoperation cycles is selected by the MUX 324 ₅ in every operation cycleout of the eight operation cycles and each of data h₂, h₁₀, h₆, h₁₄,h₁₄, h₆, h₁₀ and h₂ is output sequentially from the MUX 324 ₄ and storedinto the register 30 ₄. Data h₀, h₂, h₄, h₆, h₈, h₁₀, h₁₂ and h₁₄ outputfrom the register 22 ₁ to register 22 ₈ in every operation cycle out ofeight operation cycles is selected by the MUX 324 ₆ in every operationcycle out of the eight operation cycles and each of data h₆, h₂, h₁₄,h₁₀, h₁₀, h₁₄, h₂ and h₆ is output sequentially from the MUX 324 ₄ andstored into the register 30 ₅. Data h₀, h₂, h₄, h₆, h₈, h₁₀ of h₁₂ andh₁₄ output from the register 22 ₁ to register 22 ₈ in every operationcycle out of eight operation cycles is selected by the MUX 324 ₇ inevery operation cycle out of the eight operation cycles and each of datah₁₀, h₁₄, h₂, h₆, h₆, h₂, h₁₄ and h₁₀ is output sequentially from theMUX 324 ₇ and stored into the register 30 ₅. Data h₀, h₂, h₄, h₆, h₈,h₁₀, h₁₂ and h₁₄ output from the register 22 ₁ to register 22 ₈ in everyoperation cycle out of 8 operation cycles is selected by the MUX 324 ₈in every operation cycle out of the eight operation cycles and each ofdata h₁₄, h₆, h₁₀, h₂, h₂, h₁₀, h₆ and h₁₄ is output sequentially fromthe MUX 324 ₇ and stored into the register 30 ₇.

Data h₁, h₃, h₅, h₇, h₉, h₁₁, h₁₃ and h₁₅ output from the register 22 ₉to register 22 ₁₆ in every operation cycle out of eight operation cyclesis selected by the MUX 324 ₉ in every operation cycle out of the eightoperation cycles and each of data h₁, h₁₁, h₁₃, h₉, h₇, h₃, h₅ and h₁₅is output sequentially from the MUX 324 ₉ and stored into the register30 ₈. Data h₁, h₃, h₅, h₇, h₉, h₁₁, h₁₃ and h₁₅ output from the register22 ₉ to register 22 ₁₆ in every operation cycle out of eight operationcycles is selected by the MUX 324 ₁₂ in every operation cycle out of theeight operation cycles and each of data h₇, h₁₃, h₅, h₁, h₁₅, h₁₁, h₃and h₉ is output sequentially from the MUX 324 ₁₂ and stored into theregister 30 ₁₁. Data h₁, h₃, h₅, h₇, h₉, h₁, h₁₃ and h₁₅ output from theregister 22 ₉ to register 22 ₁₆ in every operation cycle out of eightoperation cycles is selected by the MUX 324 ₁₂ in every operation cycleout of the eight operation cycles and each of data h₉, h₃, h₁₁, h₁₅, h₁,h₅, h₁₃ and h₇ is output sequentially from the MUX 324 ₁₃ and storedinto the register 30 ₁₂. Data h₁, h₃, h₅, h₇, h₉, h₁₁, h₁₃ and h₁₅output from the register 22 ₉ to register 22 ₁₆ in every operation cycleout of eight operation cycles is selected by the MUX 324 ₁₄ in everyoperation cycle out of the eight operation cycles and each of data h₁₁,h₇, h₁₅, h₃, h₁₃, h₁, h₉ and h₅ is output sequentially from the MUX 324₁₄ and stored into the register 30 ₁₃. Data h₁, h₃, h₅, h₇, h₉, h₁₁, h₁₃and h₁₅ output from the register 22 ₉ to register 22 ₁₆ in everyoperation cycle out of eight operation cycles is selected by the MUX 324₁₅ in every operation cycle out of the eight operation cycles and eachof data h₁₃, h₁₅, h₉, h₁₁, h₅, h₇, h₁ and h₃ is output sequentially fromthe MUX 324 ₁₅ and stored into the register 30 ₁₄. Data h₁, h₃, h₅, h₇,h₉, h₁₁, h₁₃ and h₁₅ output from the register 22 ₉ to register 22 ₁₆ inevery operation cycle out of eight operation cycles is selected by theMUX 324 ₁₆ in every operation cycle out of the eight operation cyclesand each of data h₁₅, h₅, h₃, h₇, h₉, h₁₃, h₁₁ and h₁ is outputsequentially from the MUX 324 ₁₅ and stored into the register 30 ₁₅.

Each of data output from the register 30 ₁ to register 30 ₇ in everyoperation cycle out of eight operation cycles is multiplied by acorresponding coefficient P₇, P₁₁, P₃, P₁₃, P₉, P₅ and P₁ in thecorresponding fixed coefficient multiplying circuit 232 ₁ to fixedcoefficient multiplying circuit 232 ₇ in every operation cycle out ofthe eight operation cycles and stored into the register 334 ₁ toregister 334 ₇. Each of data stored into each of the correspondingregister 334 ₁ to register 334 ₇ undergoes adding operations in theadding circuit 338 ₃ in every operation cycle out of the eight operationcycles and is stored in the register 40 ₃.

Data on which adding operations are performed in a first operation cycleout of the eight operation cycles in the adding circuit 338 ₃ and whichis stored into the register 40 ₃ is(h₀+h₈)P₇+h₄P₁₁+h₁₂P₃+h₂P₁₃+h₆P₆+h₁₀P₅+h₁₄P₁. Data stored in theregister 40 ₃ in the first operation cycle is the operation value f₀+f₈in the equation (69). Data on which adding operations are performed in asecond operation cycle out of the eight operation cycles in the addingcircuit 338 ₃ and which is stored into the register 40 ₃ is(h₀−h₈)P₇−h₁₂P₁₁+h₄P₃−h₁₀P₁₃+h₂P₉−h₁₄P₅−h₆P₁. Data stored in theregister 40 ₃ in the second operation cycle is the operation value f₁+f₉in the equation (69). Data on which adding operations are performed in athird operation cycle out of the eight operation cycles in the addingcircuit 338 ₃ and which is stored into the register 40 ₃ is(h₀−h₈)P₇+h₁₂P₁₁−h₄P₃−h₆P₁₃+h₁P₉−h₂P₅+h₁₀P₁. Data stored in the register40 ₃ in the third operation cycle is the operation value f₂+f₁₀ in theequation (69). Data on which adding operations are performed in thethird operation cycle out of the eight operation cycles in the addingcircuit 338 ₃ and which is stored into the register 40 ₃ is(h₀+h₈)P₇−h₄P₁₁−h₁₂P₃+h₁₄ P₁₃+h₁₀P₉−h₆P₅+h₂P₁. Data stored in theregister 40 ₃ in the third operation cycle is the operation value f₃+f₁₁in the equation (69). Data on which adding operations are performed inthe fifth operation cycle out of the eight operation cycles in theadding circuit 338 ₃ and which is stored into the register 40 ₃ is(h₀+h₈)P₇−h₄P₁₁−h₁₂P₃+h₁₄P₁₃−h₁₀P₉+h₆P₅−h₂P₁. Data stored in theregister 40 ₃ in the fifth operation cycle is the operation value f₄+f₁₂in the equation (69). Data on which adding operations are performed inthe sixth operation cycle out of the eight operation cycles in theadding circuit 338 ₃ and which is stored into the register 40 ₃ is(h₀−h₈)P₇+h₁₂P₁₁−h₄P₃+h₆P₁₃−h₁₄P₉−h₂P₅−h₁₀P₁. Data stored in theregister 40 ₃ in the fifth operation cycle is the operation value f₅+f₁₃in the equation (69). Data on which adding operations are performed inthe seventh operation cycle out of the eight operation cycles in theadding circuit 338 ₃ and which is stored into the register 40 ₃ is(h₀−h₈)P₇−h₁₂P₁₁+h₄P₃+h₁₀P₁₃+h₂P₉+h₁₄P₅+h₆P₁. Data stored in theregister 40 ₃ in the fifth operation cycle is the operation value f₆+f₁₄in the equation (69). Data on which adding operations are performed inthe eighth operation cycle out of the eight operation cycles in theadding circuit 338 ₃ and which is stored into the register 40 ₃ is(h₀+h₈)P₇+h₄P₁₁−h₁₂P₃−h₂P₁₃−h₆P₉+h₁₀P₅+h₁₄P₁. Data stored in theregister 40 ₃ in the eighth operation cycle is the operation valuef₇+f₁₅ in the equation (69).

Each of data output from the register 30 ₈ to register 30 ₁₅ in everyoperation cycle out of eight operation cycles is multiplied by acorresponding coefficient P₁₄, P₁₂, P₁₀, P₈, P₄, P₂ and P₀ in thecorresponding fixed coefficient multiplying circuit 232 ₈ to fixedcoefficient multiplying circuit 232 ₁₅ in every operation cycle out ofthe eight operation cycles and stored into the register 334 ₈ toregister 334 ₁₅. Each of data stored into each of the correspondingregister 334 ₈ to register 334 ₁₅ undergoes adding operations in theadding circuit 338 ₄ in every operation cycle out of the eight operationcycles and is stored in the register 40 ₄.

Data on which adding operations are performed in a second operationcycle out of the eight operation cycles in the adding circuit 338 ₄ andwhich is stored into the register 40 ₃ is −h₁P₁₄+h₁P₁₂−h₉P₁₀−h₁₃P₈+h₃P₆−h₇P₄−h₁₅P₂+h₅P₀. Data stored in the register 40 ₄ in the secondoperation cycle is the operation value f₁−f₉ in the equation (69). Dataon which adding operations are performed in a third operation cycle outof the eight operation cycles in the adding circuit 338 ₄ and which isstored into the register 40 ₄ ish₁₃P₁₄−h₇P₁₂+h₁P₁₀−h₅P₈+h₁₁P₆+h₁₅P₄−h₉P₂+h₃P₀. Data stored in theregister 40 ₄ in the third operation cycle is the operation value f₂−f₁₀in the equation (69). Data on which adding operations are performed in afourth operation cycle out of the eight operation cycles in the addingcircuit 338 ₄ and which is stored into the register 40 ₄ ish₉P₁₄−h₅P₁₂−h₁₃P₁₀+h₁P₈−h₁₅P₆−h₃P₄+h₁₁P₂+h₇P₀. Data stored in theregister 40 ₄ in the fourth operation cycle is the operation valuef₃−f₁₁ in the equation (69). Data on which adding operations areperformed in a fifth operation cycle out of the eight operation cyclesin the adding circuit 338 ₄ and which is stored into the register 40 ₄is h₇P₁₄−h₁₁P₁₂−h₃P₁₀+h₁₅P₈+h₁P₆+h₁₃P₄−h₅P₂−h₉P₀. Data stored in theregister 40 ₄ in the fifth operation cycle is the operation value f₄−f₁₂in the equation (69). Data on which adding operations are performed in asixth operation cycle out of the eight operation cycles in the addingcircuit 338 ₄ and which is stored into the register 40 ₄ is−h₃P₁₄−h₉P₁₂−h₁₅P₁₀+h₁₁P₈+h₅P₆+h₁P₄+h₇P₂+h₁₃P₀. Data stored in theregister 40 ₄ in the sixth operation cycle is the operation value f₅−f₁₃in the equation (69). Data on which adding operations are performed in aseventh operation cycle out of the eight operation cycles in the addingcircuit 338 ₄ and which is stored into the register 40 ₄ ish₅P₁₄+h₁₅P₁₂−h₇P₁₀−h₃P₈−h₁₃P₆+h₉P₄+h₁P₂+h₁₁P₀. Data stored in theregister 40 ₄ in the seventh operation cycle is the operation valuef₆−f₁₄ in the equation (69). Data on which adding operations areperformed in a eighth operation cycle out of the eight operation cyclesin the adding circuit 338 ₄ and which is stored into the register 40 ₄is −h₁₅P₁₄+h₁₃P₁₂−h₁₁P₁₀+h₉P₈−h₇P₆+h₅P₄−h₃P₂+h₁P₀. Data stored in theregister 40 ₄ in the eighth operation cycle is the operation valuef₇−f₁₅ in the equation (69).

Adding operations are performed on eight pieces of data outputsequentially from the register 40 ₃ and on eight pieces of data outputsequentially from the register 40 ₄ in the adding circuit 42 and theresulting data f₀, f₁, f₂, f₃, f₄, f₅, f₆ and f₇ are output from theadding circuit 42 and then is stored sequentially into the register 46.The data f₀, f₁, f₂, f₃, f₄, f₅, f₆ and f₇ are shown in a lower part ofan output line of the register 46 in FIG. 16. Adding operations areperformed on eight pieces of data output sequentially from the register40 ₃ and on eight pieces of data output sequentially from the register40 ₄ in the adding circuit 44 and the resulting data f₈, f₉, f₁₀, f₁₁,f₁₂, f₁₃, f₁₄ and f₁₅ are output from the adding circuit 44 and then isstored sequentially into the register 46. The data f₈, f₉, f₁₀, f₁₁,f₁₂, f₁₃, f₁₄ and f₁₅ are shown in a lower part of an output line of theregister 46 in FIG. 16.

By completing the above arithmetic operations, the primary 16-16 IDCT onsixteen pieces of data in one string constituting the 16×16 data blocktransmitted after having undergone the DCT is terminated. The sameprimary 16-16 IDCT as described above is performed on each of stringssubsequent to a next string constituting the 16×16 data block andthereafter, and the primary 16-6 IDCT on all sixteen string constitutingthe 16×16 data block is terminated in the similar manner. After thecompletion of the primary 16-16 IDCT on the all sixteen strings, asecondary 16-16 IDCT is performed on each string of sixteen data stringsconstituting the 16×16 data block (transposed data for DCT). Bycompleting the secondary 16-16 IDCT, original image pictures transmittedafter having undergone the 16-16 DCT can be reproduced.

Next, the operations for the 2-8-16 IDCT will be explained.

Each of sixteen pieces of picture element data f₀ to picture elementdata f₁₅ contained in each string constituting the block composed of16×16 pieces of data transmitted after having undergone the 16-16 DCT onthe 16×16 picture elements sequentially from the MUX 312, is stored intoeach of register 14 ₁ to register 14 ₁₆ constituting the first registergroup 313 which corresponds to each of sixteen pieces of data F₀ to dataF₁₅.

Data F₀ out of sixteen pieces of data F₀ to data F₁₅ is stored into theregister 14 ₁ constituting a first register group 313, data F₈ into theregister 14 ₂, data F₁ into the register 14 ₃, data F₉ into the register14 ₄, data F₂ into the register 14 ₅, data F₁₀ into the register 14 ₆,data F₃ into the register 14 ₇, data F₁₁ into the register 14 ₈, data F₅into the register 14 ₉, data F₁₃ into the register 14 ₁₀, data F₆ intothe register 14 ₁₁, data F₁₄ into the register 14 ₁₂, data F₇ into theregister 14 ₁₃, data F₁₅ into the register 14 ₁₄, data F₄ into theregister 14 ₁₅ and data F₁₂ into the register 14 ₁₆.

Since the MUXs 16 ₁ to 16 ₈, 16 ₉₂, 16 ₁₀₂, 16 ₁₁₂, 16 ₁₂₂, 16 ₁₃₂, 16₁₄₂, 16 ₁₅₂ and 16 ₁₆₂ have selected the registers 14 ₂, 14 ₄, 14 ₆, 14₈, 14 ₁₀, 14 ₁₂, 14 ₁₄ and 14 ₁₆ respectively, and the MUX 16 ₉₁, 16₁₀₁, 16 ₁₁₁, 16 ₁₂₁, 16 ₁₃₁, 16 ₁₄₁, 16 ₁₅₁ and 16 ₁₆₁ have selected theregisters 14 ₁, 14 ₃, 14 ₅, 14 ₇, 14 ₉, 14 ₁₁, 14 ₁₃ and 14 ₁₄respectively, data F₀+F₈=i₀ is output from the adding circuit 18 ₁, dataF₁+F₉=i₁ from the adding circuit 18 ₂, data F₂+F₁₀=i₂ from the addingcircuit 18 ₃, data F₃+F₁₁=i₃ from the adding circuit 18 ₄, dataF₅+F₁₃=i₄ from the adding circuit 18 ₅, data F₆+F₁₄=i₅ from the addingcircuit 18 ₆, data F₇+F₁₅=i₆ from the adding circuit 18 ₇, dataF₄+F₁₂=i₇ from the adding circuit 18 ₈, F₀−F₈=i₈ from the subtractingcircuit 20 ₁, data F₁−F₉=i₉ from the subtracting circuit 20 ₂,F₂−F₁₀=i₁₀ from the subtracting circuit 20 ₃, data F₃−F₁₁=i₁₁ from thesubtracting circuit 20 ₄, data F₅−F₁₃=i₁₂ from the subtracting circuit20 ₅, data F₆−F₁₄=i₁₃ from the subtracting circuit 20 ₆, F₇−F₁₅=i₁₄ fromthe subtracting circuit 20 ₇ and F₄−F₁₂=i₁₅ from the subtracting circuit20 ₈.

Data i₀ output from the adding circuit 18 ₁ is stored into the register22 ₁, data i₁ is output from the adding circuit 18 ₂ is stored into theregister 22 ₂, data i₂ output from the adding circuit 18 ₃ is storedinto the register 22 ₃, data i₃ output from the adding circuit 18 ₄ isstored into the register 22 ₄, data i₄ output from the adding circuit 18₅ is stored into the register 22 ₅, data i₅ output from the addingcircuit 18 ₆ is stored into the register 22 ₆, data i₆ output from theadding circuit 18 ₇ is stored into the register 22 ₇ and data i₇ outputfrom the adding circuit 18 ₈ is stored into the register 22 ₈.

Data i₈ output from the subtracting circuit 20 ₁ is stored into theregister 22 ₉, data i₉ output from the subtracting circuit 20 ₂ isstored into the register 22 ₁₀, data i₁₀ output from the subtractingcircuit 20 ₃ is stored into the register 22 ₁₁, data i₁₁ output from thesubtracting circuit 20 ₄ is stored into the register 22 ₁₂, data i₁₂output from the subtracting circuit 20 ₅ is stored into the register 22₁₃, data i₁₃ output from the subtracting circuit 20 ₆ is stored into theregister 22 ₁₄, data i₁₄ output from the subtracting circuit 20 ₇ iSstored into the register 22 ₁₅ and data i₁₅ output from the subtractingcircuit 20 ₈ is stored into the register 22 ₁₆.

Data i₀ to data i₈ output from the register 22 ₁ to register 22 ₈ inevery operation cycle out of eight operation cycles is selected in theMUX 324 ₁ in every operation cycle out of the eight operation cycles,and the data i₀ is output sequentially from the MUX 324 ₁ eight timesand is fed to the adding/subtracting circuit 326 ₁. Data i₀ to data i₇output from the register 22 ₁ to register 22 ₈ in every operation cycleout of eight operation cycles is selected in the MUX 324 ₂ in everyoperation cycle out of the eight operation cycles, and the data i₇ isoutput sequentially from the MUX 324 ₂ eight times and is fed to theadding/subtracting circuit 326 ₁ and each of data i₀+i₇, i₀−i₇, i₀−i₇,i₀+i₇, i₀+i₇, i₀−i₇, i₀−i₇ and i₀+i₇ is output sequentially from theadding/subtracting circuit 326 ₁ in every operation cycle out of theeight operation cycles and stored into the register 30 ₁.

Each of data i₀ to data i₇ output from the register 22 ₁ to register 22₈ in every operation cycle out of eight operation cycles is selected inthe MUX 324 ₃ in every operation out of the eight operation cycles andeach of data i₂, i₅, i₅, i₂, i₂, i₅, i₅ and i₂ is output sequentiallyand stored into the register 30 ₂. Each of data i₀ to data i₇ outputfrom the register 22 ₁ to register 22 ₈ in every operation cycle out ofthe eight operation cycles is selected in the MUX 324 ₄ in everyoperation out of the 8 operation cycles and each of data i₅, i₂, i₂, i₅,i₅, i₂, i₂ and i₅ is output sequentially and stored into the register 30₃. Each of data i₀ to data i₇ output from the register 22 ₁ to register22 ₈ in every operation cycle out of the eight operation cycles isselected in the MUX 324 ₅ in every operation out of the eight operationcycles and each of data i₁, i₄, i₃, i₆, i₆, i₃, i₄ and i₁ is outputsequentially and stored into the register 30 ₄. Each of data i₀ to datai₇ output from the register 22 ₁ to register 22 ₈ in every operationcycle out of the eight operation cycles is selected in the MUX 324 ₆ inevery operation out of the eight operation cycles and each of data i₃,i₁, i₆, i₄, i₄, i₆, i₁ and i₃ is output sequentially and stored into theregister 30 ₅. Each of data i₀ to i₇ output from the register 22 ₁ toregister 22 ₈ in every operation cycle out of the eight operation cyclesis selected in the MUX 324 ₇ in every operation out of the eightoperation cycles and each of data i₄, i₆, i₁, i₃, i₃, i₁, i₆ and i₄ isoutput sequentially and stored into the register 30 ₆. Each of data i₀to data i₇ output from the register 22 ₁ to register 22 ₈ in everyoperation cycle out of the eight operation cycles is selected in the MUX324 ₈ in every operation out of the eight operation cycles and each ofdata i₆, i₃, i₄, i₁, i₁, i₄, i₃ and i₆ is output sequentially and storedinto the register 30 ₇.

Each of data i₈ to data i₁₅ output from the register 22 ₉ to register 22₁₆ in every operation cycle out of eight operation cycles is selected inthe MUX 324 ₉ in every operation cycle out of the eight operationcycles, and data i₈ is sequentially output from the MUX 324 ₉ eighttimes and fed to the adding/subtracting circuit 326 ₁ while each of datai₈ to data i₁₅ output from the register 22 ₉ to register 22 ₁₆ isselected in the MUX 324 ₁₆ in every operation cycle out of the eightoperation cycles and data i₁₅ is sequentially output from the MUX 324 ₁₆eight times and is fed to the adding/subtracting circuit 326 ₁, and eachof data i₈+i₁₅, data i₈−i₁₅, data i₈−i₁₅, data i₈+i₁₅, data i₈+i₁₅, datai₈−i₁₅ and data i₈+i₁₅ is output sequentially in every operation cycleout of the eight operation cycles and stored into the register 30 ₈through the MUX 28 ₁.

Each of data i₈ to data i₁₅ output from the register 22 ₉ to register 22₁₆ in every operation cycle out of eight operation cycles is selected inthe MUX 324 ₁₀ in every operation cycle out of the eight operationcycles and each of data i₁₀, i₁₃, i₁₃, i₁₀,i₁₀, i₁₃, i₁₃ and i₁₀ isoutput sequentially from the MUX 324 ₁₀ and stored into the register 30₉.

Each of data i₈ to data i₁₅ output from the register 22 ₉ to register 22₁₆ in every operation cycle out of eight operation cycles is selected inthe MUX 324 ₁₁ in every operation cycle out of the eight operationcycles and each of data i₁₃, i₁₀, i₁₀, i₁₃, i₁₃, i₁₀, i₁₀ and i₁₃ isoutput sequentially from the MUX 324 ₁₁ and stored into the register 30₁₀. Each of data i₈ to data i₁₅ output from the register 22 ₉ toregister 22 ₁₆ in every operation cycle out of eight operation cycles isselected in the MUX 324 ₁₂ in every operation cycle out of the 8operation cycles and each of data i₉, i₁₂, i₁₁, i₁₄, i₁₄, i₁₁, i₁₂ andi₁₅ output sequentially from the MUX 324 ₁₂ and stored into the register30 ₁₁. Each of data i₈ to data i₁₅ output from the register 22 ₉ toregister 22 ₁₆ in every operation cycle out of eight operation cycles isselected in the MUX 324 ₁₂ in every operation cycle out of the eightoperation cycles and each of data i₉, i₁₂, i₁₁, i₁₄, i₁₄, i₁₁, i₁₂ andi₉ is output sequentially from the MUX 324 ₁₂ and stored into theregister 30 ₁₁. Each of data i₈ to data i₁₅ output from the register 22₉ to register 22 ₁₆ in every operation cycle out of eight operationcycles is selected in the MUX 324 ₁₄ in every operation cycle out of theeight operation cycles and each of data i₁₂, i₁₄, i₉, i₁₁, i₁₁, i₁₉, i₁₄and i₁₂ is output sequentially from the MUX 324 ₁₃ and stored into theregister 30 ₁₁.

Each of data i₈ to data i₁₅ output from the register 22 ₉ to register 22₁₆ in every operation cycle out of eight operation cycles is selected inthe MUX 324 ₁₅ in every operation cycle out of the eight operationcycles and each of data i₁₄, i₁₁, i₁₂, i₉, i₉, i₁₂, i₁₁ and i₁₄ isoutput sequentially from the MUX 324 ₁₅ and stored into the register 30₁₅ through the MUX 28 ₃. Since the MUX 28 ₂ has selected “0” data, alldata output from the MUX 324 ₁₅ are stored as “0” data into the register334 ₁₄.

Each of data output from the register 30 ₁ to register 30 ₇ in everyoperation cycle out of eight operation cycles undergoes addingoperations in the adding circuit 338 ₃ in every operation cycle out ofthe eight operation cycles and is stored into the register 40 ₃. Datathat undergoes adding operations in the adding circuit 338 ₃ in a firstoperation cycle out of the eight operation cycles and is stored in theregister 40 ₃ is (i₀+i₇)P₇+i₂P₁₁+i₅P₃+i₁P₁₃+i₁₃P₉+i₄P₅+i₆P₁. Data storedinto the register 40 ₃ in the first operation cycle represents theoperation value f₀ in the equation (70) which is shown as f₀ in a lowerpart of the output line of the register 40 ₃ in FIG. 16. Data thatundergoes adding operations in the adding circuit 338 ₃ in a secondoperation cycle out of the eight operation cycles and is stored in theregister 40 ₃ is (i₀−i₇)P₇−i₅P₁₁+i₂P₃−i₄P₁₃+i₁P₉−i₆P₅−i₃P₁. Data storedinto the register 40 ₃ in the second operation cycle represents theoperation value f₀ in the equation (70) which is shown as f₂ in a lowerpart of an output line of the register 40 ₃ in FIG. 16. Data thatundergoes adding operations in the adding circuit 338 ₃ in a thirdoperation cycle out of the eight operation cycles and is stored in theregister 40 ₃ is (i₀−i₇)P₇+i₅P₁₁−i₂P₃−i₃P₁₃+i₆P₉+i₁P₅+i₄P₁. Data storedinto the register 40 ₃ in the third operation cycle represents theoperation value f₄ in the equation (70) which is shown as f₂ in a lowerpart of an output line of the register 40 ₃ in FIG. 16. Data thatundergoes adding operations in the adding circuit 338 ₃ in a fourthoperation cycle out of the eight operation cycles and is stored in theregister 40 ₃ is (i₀+i₇)P₇−i₂P₁₁−i₅P₃−i₆P₁₃+i₄P₉−i₃P₅+i₁P₁. Data storedinto the register 40 ₃ in the fourth operation cycle represents theoperation value f₆ in the equation (70) which is shown as f₆ in a lowerpart of the output line of the register 40 ₃ in FIG. 16. Data thatundergoes adding operations in the adding circuit 338 ₃ in a fifthoperation cycle out of the eight operation cycles and is stored in theregister 40 ₃ is (i₀+i₇)P₇−i₂P₁₁−i₅P₃−i₆P₁₃−i₄P₉+i₃P₅−i₁P₁. Data storedinto the register 40 ₃ in the fifth operation cycle represents theoperation value f₈ in the equation (70) which is shown as f₈ in thelower part of the output line of the register 40 ₃ in FIG. 16. Data thatundergoes adding operations in the adding circuit 338 ₃ in a sixthoperation cycle out of the eight operation cycles and is stored in theregister 40 ₃ is (i₀−i₇)P₇+i₅P₁₁−i₂P₃+i₆P₁₃−i₆P₉−i₁P₅−i₄P₁. Data storedinto the register 40 ₃ in the sixth operation cycle represents theoperation value f₁₀ in the equation (70) which is shown as f₁₀ in thelower part of the output line of the register 40 ₃ in FIG. 16. Data thatundergoes adding operations in the adding circuit 338 ₃ in a seventhoperation cycle out of the eight operation cycles and is stored in theregister 40 ₃ is (i₀−i₇)P₇−i₅P₁₁+i₂P₃+i₄P₁₃−i₁P₉+i₆P₅+i₃P₁. Data storedinto the register 40 ₃ in the sixth operation cycle represents theoperation value f₁₂ in the equation (70) which is shown as f₁₂ in thelower part of the output line of the register 40 ₃ in FIG. 16. Data thatundergoes adding operations in the adding circuit 338 ₃ in an eighthoperation cycle out of the eight operation cycles and is stored in theregister 40 ₃ is (i₀+i₇)P₇+i₂P₁₁−i₅P₃−i₁P₁₃−i₃P₉−i₄P₅−i₆P₁. Data storedinto the register 40 ₃ in the eighth operation cycle represents theoperation value f₁₄ in the equation (70) which is shown as f₁₄ in thelower part of the output line of the register 40 ₃ in FIG. 16.

Each of data output from the register 334 ₈ to register 334 ₁₅ in everyoperation cycle out of eight operation cycles undergoes addingoperations in the adding circuit 338 ₄ in every operation cycle out ofthe eight operation cycles and is stored into the register 40 ₄.

Data that undergoes adding operations in the adding circuit 338 ₄ in afirst operation cycle out of the eight operation cycles and is stored inthe register 40 ₄ is (i₈+i₁₅)P₇+i₁₀P₁₁+i₁₃P₃+i₉P₁₃+i₁₁P₉+i₁₂P₅+i₁₄P₁.Data stored into the register 40 ₄ in the first operation cyclerepresents the operation value f₁ in the equation (70) which is shown asf₁ in a lower part of the output line of the register 40 ₄ in FIG. 16.Data that undergoes adding operations in the adding circuit 338 ₄ in asecond operation cycle out of the eight operation cycles and is storedin the register 40 ₄ is (i₈−i₅)P₇−i₁₃P₁₁+i₁₀P₃−i₁₂P₁₃+i₉P₉−i₁₄P₅−i₁₄P₁.Data stored into the register 40 ₄ in the first operation cyclerepresents the operation value f₃ in the equation (70) which is shown asf₃ in the lower part of the output line of the register 40 ₄ in FIG. 16.Data that undergoes adding operations in the adding circuit 338 ₄ in athird operation cycle out of the eight operation cycles and is stored inthe register 40 ₄ is (i₈−i₁₅)P₇+i₁₃P₁₁−i₁₀P₃−i₁₁P₁₃+i₁₄P₉+i₉P₅+i₁₂P₁.Data stored into the register 40 ₄ in the first operation cyclerepresents the operation value f₅ in the equation (70) which is shown asf₅ in the lower part of the output line of the register 40 ₄ in FIG. 16.Data that undergoes adding operations in the adding circuit 338 ₄ in afourth operation cycle out of the eight operation cycles and is storedin the register 40 ₄ is (i₈+i₁₅)P₇−i₁₀P₁₁−i₁₃P₃−i₁₄P₁₃+i₁₂P₉−i₁₁P₅+i₉P₁.Data stored into the register 40 ₄ in the fourth operation cyclerepresents the operation value f₇ in the equation (70) which is shown asf₇ in the lower part of the output line of the register 40 ₄ in FIG. 16.Data that undergoes adding operations in the adding circuit 338 ₄ in afifth operation cycle out of the eight operation cycles and is stored inthe register 40 ₄ is (i₈+i₁₅)P₇−i₁₀P₁₁−i₁₃P₃+i₁₄P₁₃−i₁₂P₉+i₁₁P₅−i₉P₁.Data stored into the register 40 ₄ in the fifth operation cyclerepresents the operation value f₉ in the equation (70) which is shown asf₉ in the lower part of the output line of the register 40 ₄ in FIG. 16.Data that undergoes adding operations in the adding circuit 338 ₄ in asixth operation cycle out of the eight operation cycles and is stored inthe register 40 ₄ is (i₈−i₁₅)P₇+i₁₃P₁₁−i₁₀P₃+i₁₁P₁₃−i₁₄P₉−i₉P₅−i₁₂P₁.Data stored into the register 40 ₄ in the sixth operation cyclerepresents the operation value f₁₁ in the equation (70) which is shownas f₁₁ in the lower part of the output line of the register 40 ₄ in FIG.16. Data that undergoes adding operations in the adding circuit 338 ₄ ina seventh operation cycle out of the eight operation cycles and isstored in the register 40 ₄ is(i₈−i₁₅)P₇−i₁₃P₁₁+i₁₀P₃+i₁₂P₁₃−i₉P₉+i₁₄P₅+i₁₁P₁. Data stored into theregister 40 ₄ in the seventh operation cycle represents the operationvalue f₁₃ in the equation (70) which is shown as f₁₃ the a lower part ofthe output line of the register 40 ₄ in FIG. 16. Data that undergoesadding operations in the adding circuit 338 ₄ in an eighth operationcycle out of the eight operation cycles and is stored in the register 40₄ is (i₈+i₁₅)P₇+i₁₀P₁₁+i₁₃P₁₃−i₉P₁₃−i₁₁P₉−i₁₂P₅−i₁₄P₁. Data stored intothe register 40 ₄ in the eighth operation cycle represents the operationvalue f₁₅ in the equation (70) which is shown as f₁₅ in the lower partof the output line of the register 40 ₄ in FIG. 16.

By completing the above arithmetic operations, the primary 2-8-16 IDCTon sixteen pieces of data in one string constituting the 16×16 datablock transmitted after having undergone the 2-8-16 DCT is terminated.The same primary 2-8-16 IDCT as described above is performed on each ofstrings subsequent to a next string constituting the 16×16 data blockand thereafter, and the primary 2-8-16 IDCT on all sixteen stringconstituting the 16×16 data block is terminated in the similar manner.After the completion of the primary 2-8-16 IDCT on the all sixteenstrings, a secondary 2-8-16 IDCT is performed on each string of sixteendata strings constituting the 16×16 data block (transposed data forDCT). By completing the primary 2-8-16 IDCT and secondary 2-8-16 IDCT oneach 16×16 data, original image pictures transmitted after havingundergone the 2-816 DCT can be reproduced.

Thus, according to the present invention, since the 16-16 IDCT and2-8-16 IDCT device are so configured that a part of the fixedcoefficient multiplying circuit used in the 16-16 IDCT circuit can beused, by being switched, as a fixed coefficient multiplying circuitrequired in the 2-8-16 DCT, a high-speed calculating characteristicobtained through the pipeline processing type arithmetic operation inthe 16-16 IDCT can be maintained in the 2-8-16 IDCT and the high-speedcalculating characteristic can be still maintained in even miniaturized16-16 IDCT devices and 2-8-16 IDCT devices.

Based on the above first embodiment to fourth embodiment, followingconclusions can be drawn:

An equation (74) can be obtained by developing an equation (73) andarranging it with respect to “N” in the same manner as in the case ofthe first embodiment and third embodiment. Therefore, by performing anoperation expressed by the equation (74) to each line and each stringconstituting the 2^(N)×2^(N) picture element data in the same manner asin the case of the first embodiment and second embodiment, an operationfor 2−2^(N−1)−2^(N) DCT can be performed. $\begin{matrix}\left. \begin{matrix}\begin{matrix}{{F\left( {h,v} \right)} = \quad {{C(v)}{C(h)}{\sum\limits_{z = 0}^{2^{N - 1} - 1}{\sum\limits_{x = 0}^{N}\left\{ {{f\left( {x,{2z}} \right)} +} \right.}}}} \\{\left. \quad {f\left( {x,{{2z} + 1}} \right)} \right\} \cos \quad {\delta \cdot \cos}\quad ɛ}\end{matrix} \\\begin{matrix}{{F\left( {h,{v + 4}} \right)} = \quad {{C(v)}{C(h)}{\sum\limits_{z = 0}^{2^{N - 1} - 1}{\sum\limits_{x = 0}^{N}\left\{ {{f\left( {x,{2z}} \right)} +} \right.}}}} \\{\left. \quad {f\left( {x,{{2z} + 1}} \right)} \right\} \cos \quad {\delta \cdot \cos}\quad ɛ}\end{matrix}\end{matrix} \right\} & (73)\end{matrix}$

where

v=0, 1, . . . ; 7

z=integer of y/2

First, matrices in the right position on the right side in the equation(74) are described.

Out of components contained in the matrix in the right position on theright side in the equation (74), components given with final numbers P₁,P₅, P₉, P₁₃, . . . , and components expressed in the equation (75) arecoefficients obtained by selecting every other “i” having cases wherei=1 to i=2^(N−1)−1, where the coefficients are expressed as the fixedcoefficient Pi (i=0, 1, 2, . . . , 2^(N−1)−1) as shown in the equation(76). By selecting the coefficient which can be obtained when i=2^(N)−3to i=2^(N−1)−1 by choosing every other “1” which is left after selectingthe coefficients except the fixed coefficients obtained by choosingevery other “1” where i=1 to i=2^(N−1)−1 and consequently by selectingthe fixed coefficient obtained by choosing every other “1” which isstill left and, thereafter, each component contained in the matrices inthe right position in the right side in the equation (74) can bedetermined. In the present application, the fixed coefficient that canbe determined as above is called “a fixed coefficient that can bedetermined according to a discrete cosine transformation rule.”

P₂ _(^(N)) ⁻³  (75)

$\begin{matrix}\left. \begin{matrix}{P_{i} = {\cos \left( \frac{\left( {N - 1 - i} \right)\pi}{2^{N + 1}} \right)}} \\\begin{pmatrix}{0 \leqq k \leqq {2^{N - 1} - 2}} \\{{\text{where}\quad k} = {2^{N - 1} - {1\quad \text{is excluded;}}}}\end{pmatrix} \\{P_{2^{N - 1} - 1} = \frac{1}{\sqrt{2}}} \\\left( {k = {2^{N - 1} - 1}} \right)\end{matrix} \right\} & (76)\end{matrix}$

A first string on a first line contained in a matrix existing on anupper side in a left position on the right side in the equation (74) isgiven by an equation (77) and each term of values kj (j=0, 1, 2, . . . ,2^(N−1)−1) in the equation (77) is given by an equation (78).

A first string on a first line contained in a matrix existing on a lowerside in a left position on the right side in the equation (74) is givenby an equation (79) and each term of values kj (j=2^(N−1), 2^(N−1)+1,2^(N−1)+2, . . . , 2^(N)−1) in the equation (79) is given by an equation(80).

A cell shown in the equation (74) out of each component in the matrix onan upper side in the left position on the left side in the equation (74)represents one component. All of components not shown by the cell are“0”. As shown in the equation (74), a first string on the second line isone component.

Frames shown by “2¹×2¹” to a frame shown by “2^(N−3)×2^(N−3)” arearranged toward a lower right direction, and from the frame shown“2^(N−3)×2^(N−3)” to another frame shown by “2^(N−2)×2^(N−2)” arearranged toward a lower right direction.

Components 2¹×2¹ (2¹×2¹ pieces of cells) are contained in the frameshown by “2¹×2¹”, that is, by the third line and fourth line and by thesecond string and third string. Components 2²×2² (2²×2² pieces of cells)are contained in the frame shown by “2²×2²”, that is, by the fifth lineand eighth line and by the fourth string and seventh string. Components2^(N−3)×2^(N−3) (2^(N−3)×2^(N−3) pieces of cells) are contained in theframe shown by “2^(N−3)×2^(N−3)”. Components 2^(N−2)×2^(N−2)(2^(N−2)×2^(N−2) pieces of cells) are contained in the frame shown by“2^(N−3)×2^(N−3)”.

k ₀ +k ₁ +k ₂ + . . . +k ₂ _(^(N−1)) ⁻¹  (77)

k ₀ =f ₀ +f ₁ , k ₁ =f ₂ +f ₃ , k ₂ =f ₄ +f ₅ , . . . , k ₂ _(^(N−1)) =f₂ _(^(N)) ⁻¹  (78)

k ₂ _(^(N−1)) +k ₂ _(^(N−1)) ₊₁ +k ₂ _(^(N−1)) ₊₁ + . . . +k ₂ _(^(N))⁻¹  (79)

k ₂ _(^(N−1)) =f ₀ −f ₁ , k ₂ _(^(N−1)) ₊₁ =f ₂ −f ₃ , k ₂ _(^(N−1)) ₊₂=f ₄ −f ₅ , . . . , k ₂ _(^(N)) ⁻¹ =f ₂ _(^(N)) ⁻² +f ₂ _(^(N))⁻¹}  (80)

Each of components composed of the second line and first string in thematrix on an upper side in the equation (74) and each of componentscontained in each of the frame shown by “2¹×2¹” to the frame shown by2^(N−2)×2^(N−2) is given by an adding and subtracting equation[kjm]_(N−2) (a value other than a subscript j selected out of m=j) ofeach kj expressed by the equation (78). Moreover, each of componentscomposed of the second line and first string in the matrix on a lowerside in the equation (74) and each of components contained in each ofthe frame shown by “2¹×2¹” to the frame shown by 2^(N−2)×2^(N−2) isgiven by an adding and subtracting equation [kjn]_(N−2) (a value otherthan a subscript j selected out of m=j) of each kj expressed by theequation (80).

Operations of determinants in a matrix in the left position on the rightside and in the right position on the right side in the equation (74)will be described. The component on the first line and first string andon the second line and first string is multiplied by a first componentin the matrix on the right side. Each component in each string containedin the frame shown by 2¹×2¹ is multiplied by the second component and bythe third component in the matrix on the right side. Each component ineach string contained in the frame shown by 2²×2² is multiplied by thefourth component to seventh component in the matrix on the right side.Each component in each string contained in the frame shown by2^(N−3)×2^(N−3) is multiplied by the 2^(N−3)-th to (1+2¹+2²+ . . . ,2^(N−4))-th component in the matrix on the right side. This relation canbe applied to the matrix on the upper side and on the lower side.

A sum of each product of each of components obtained in each line byoperations of the determinant of the matrix in the left position on theright side and of the matrix in the right position on the right side inthe equation (74) represents a component (transformation coefficientdata, that is, data shown as F in the equation (74)) corresponding to adeterminant shown on the right side in the equation (74).

Each component to be multiplied by the fixed coefficient Pi with oddnumbers described above is picture element data (that is, data shown as“f” in the equation (78) and equation (80)).

Though it is impossible to express which component out of kjconstituting the matrix described above comes by a general formulaand/or general expression form. However, in the same manner as done inthe equation (51) and equation (66), by developing and rearranging theequation (73) with respect to a specified value of N, the abovedescribed adding and subtracting equation [Kjm]_(N−2) and adding andsubtracting equation [kjn]_(N−2) can be determined for the specifiedvalue of N.

Also, in the case of the transformation coefficient data being 32×32, inthe same manner as done in the second embodiment and fourth embodiment,by obtaining the equation (82) by developing and rearranging theequation (81) with respect to N and by performing the operationexpressed in the equation (82) to data contained in each line or eachstring of the 2^(N)×2^(N) transformation coefficient data in the samemanner as in the second embodiment and fourth embodiment, operations forthe 2−2^(N−1)−2^(N) IDCT can be performed. The number N expressed in theequation (82) is a natural number. The matrix shown on the left side inthe determinant on the upper side in the equation (82) is pictureelement with odd numbers and the matrix shown on the left side in thedeterminant on the lower side in the equation (82) is picture elementwith even numbers.

The first string of the matrix [lop] on the upper side in the leftposition on the right side in the equation (82) and the matrix [loq] onthe lower side is expressed as a sum or difference between thetransformation coefficient data F₀ and the equation (83) while othercomponent is expressed by a matrix having component F_(k)(1≦k≧2^(N−1)−2)excluding the transformation coefficient data expressed in the equation(83). $\begin{matrix}\left. \begin{matrix}{{f\left( {x,{2z}} \right)} = {\sum\limits_{z = 0}^{2^{N - 1} - 1}{\sum\limits_{x = 0}^{N}{\left\{ {{C(v)}{C(h)}\left( {{F\left( {h,v} \right)} + {F\left( {h,{v + 4}} \right)}} \right)} \right\} \cos \quad {\delta \cdot \cos}\quad ɛ}}}} \\{{f\left( {x,{{2z} + 1}} \right)} = {\sum\limits_{y = 0}^{2^{N - 1} - 1}{\sum\limits_{x = 0}^{N}{\left\{ {{C(v)}{C(h)}\left( {{F\left( {h,v} \right)} - {F\left( {h,{v + 4}} \right)}} \right)} \right\} \cos \quad {\delta \cdot \cos}\quad ɛ}}}}\end{matrix} \right\} & (81)\end{matrix}$

where

v=0, 1, . . . , 7

z=integer of y/2 $\begin{matrix}\left. {{{{{C(h)} = {\frac{1}{2\sqrt{2}}\quad \left( {h = 0} \right)}},\quad {{C(v)} = {\frac{1}{2\sqrt{2}}\quad \left( {v = 0} \right)}}}{{{C(h)} = {\frac{1}{2}\quad \left( {{h = 1},2,\ldots \quad,7} \right)}},\quad {{C(v)} = {\frac{1}{2}\quad \left( {{v = 1},2,\ldots \quad,7} \right)}}}{{\delta \equiv \frac{\pi \quad {v\left( {{2z} + 1} \right)}}{N/2}},\quad {ɛ \equiv \frac{\pi \quad {h\left( {{2x} + 1} \right)}}{N}}}}\begin{matrix}{{2^{N - 1}\left\{ {\begin{bmatrix}f_{0} \\f_{2} \\f_{4} \\f_{6} \\\vdots \\f_{2^{N - 1} - 2}\end{bmatrix} = {\overset{2^{N - 1} - 1}{\overset{}{\begin{bmatrix}\quad & \ldots & \quad \\\quad & \left\lbrack l_{op} \right\rbrack & \quad \\\quad & \ldots & \quad\end{bmatrix}}}\quad\begin{bmatrix}P_{\frac{N}{2} - 1} \\\vdots \\P_{2^{N} - 3} \\\vdots \\P_{13} \\P_{9} \\P_{5} \\P_{1}\end{bmatrix}}} \right\} 2^{N - 1}} - 1} \\{{2^{N - 1}\left\{ {\begin{bmatrix}f_{1} \\f_{3} \\f_{5} \\f_{7} \\\vdots \\f_{1^{N - 1} - 1}\end{bmatrix} = {\overset{2^{N - 1} - 1}{\overset{}{\begin{bmatrix}\quad & \ldots & \quad \\\quad & \left\lbrack l_{oq} \right\rbrack & \quad \\\quad & \ldots & \quad\end{bmatrix}}}\quad\begin{bmatrix}P_{\frac{N}{2} - 1} \\\vdots \\P_{2^{N} - 3} \\\vdots \\P_{13} \\P_{9} \\P_{5} \\P_{1}\end{bmatrix}}} \right\} 2^{N - 1}} - 1}\end{matrix}} \right\} & (82)\end{matrix}$

 F₂ _(^(N−1)) ⁻¹  (83)

The 2^(N)-2^(N) DCT is performed in accordance with an equation (84) andthe 2^(N)-2^(N) IDCT in accordance with an equation (85). Bothcharacters and notation used in the matrix on the left side and theright side in the equation (84) and those used in the matrix on the leftside and the right side in the equation (85) correspond almost toequation (74) and equation (82). Each of components contained in thematrix in the left position on the right side in the equation (84) andequation (85) differs from that in the equation (74) and equation (82)as shown below:

Each of components [A_(st)]_(N−2) and [B_(su)]_(N−1) contained in theequation (84) is given by an equation (86). The meanings of s, t and uused in each of the components [A_(st)]_(N−2) and [B_(su)]_(N−1)contained in the equation (84) correspond to those of j, m and n. Thepicture element data f₀ to f_(2N−1) are picture element data given inthe equation (86). Each of components [C_(Vw)] and [D_(vx)] is given asthe transformation coefficient data in the 2^(N)-2^(N) IDCT. Themeanings of v, w and x used in each of the components [C_(vw)] and[D_(vx)] contained in the equation (85) correspond to those of o, p andq in the equation (82).

 a ₀ =f ₀ +f ₂ _(^(N)) ⁻¹ , a ₁ =f ₁ +f ₂ _(^(N)) ⁻² , . . . , a ₂_(^(N−1)) ⁻¹ =f ₂ _(^(N−1)) ⁻¹ +f ₂ _(^(N−1)) ,

a ₂ _(^(N−1)) =f ₀ −f ₂ _(^(N)) ⁻¹ =f ₁ +f ₂ _(^(N)) ⁻² , . . . , a ₂_(^(N)) ⁻¹ =f ₂ _(^(N−1)) ⁻¹ +f ₂ _(^(N−1)) }  (86)

f ₂ _(^(N−1))   (87)

Therefore, by using a part of the circuit used to perform the2^(N)-2^(N) DCT, the 2−2^(N−1)−2^(N) DCT can be carried out on the2^(N)-2^(N) picture element data. Also, by using a part of the circuitused to perform the 2^(N)-2^(N) IDCT, the 2−2^(N−1)−2^(N) IDCT can becarried out on the 2^(N)-2^(N) transformation coefficient data.

As described above, according to the present invention, by selecting afirst set of picture element data and second set of picture element datacomposed of 2^(N) pieces of picture element data to be multiplied by afixed coefficient Pk (0≦k≦2^(N)−1) with k having an odd number which isdetermined in accordance with the discrete cosine transformation rule,in a same order or in a different order, from 2^(N) pieces of pictureelement data contained in one line or one string out of 2^(N)×2^(N) (Nis a natural number) pieces of picture element data, by multiplying boththe selected first set of picture element data, by multiplying both theselected element data corresponding to the fixed coefficient with khaving the odd number by the fixed coefficient with k having the oddnumber to produce a product, by adding the product to the correspondingfixed coefficient, and by outputting, based on the added values, apredetermined number of transformation coefficient data out oftransformation coefficient data Pk corresponding to the added value, the2−2^(N−1)−2^(N) DCT can be performed at a high speed in a pipelineformat.

The 2−2^(N−1)−2^(N) IDCT, since it is configured in the same manner asin the case of the 2−2^(N−1)−2^(N) DCT, can be performed on the2^(N)×2^(N) pieces of transformation coefficient data.

It is apparent that the present invention is not limited to the aboveembodiments but may be changed and modified without departing from thescope and spirit of the invention. For example, when not only 32×32pieces of picture element data but also 32×32 pieces of transformationcoefficient data are used, the same effects as attained in the firstembodiment to fourth embodiment can be achieved. Moreover, in the abovefirst embodiment, the operations for both the 8-8 DCT and 2-4-8 DCT aredescribed, in the second embodiment, operations for both the 8-8 IDCTand 2-4-8 IDCT are described, in the third embodiment, operations forboth the 16-16 DCT and 2-8-16 IDCT are described and in the fourthembodiment, operations for both the 16-16 DCT and 2-8-16 IDCT aredescribed. However, the 2-4-8 DCT, 2-4-8 IDCT, 2-8-16 DCT and 2-8-16IDCT can be performed singly and independently. Also, the 8-8 DCT, 2-4-8DCT, 8-8 IDCT and 2-4-8 IDCT can be performed in one device by switchingthe MUX and codes of data output from the register without using aseparate device. If a discrete cosine transformation speed of the imagesignal is not of great importance, the above operations for the DCT andIDCT can be performed by software. The timing before operations andafter operations in the MUX in each of the embodiment described above,for example, the timing of inputting to the MUX 24 ₁ to MUX 24 ₈ and thetiming of operations subsequent to the inputting of the MUX 24 ₁ to MUX24 ₈ can be 1:2^(N−1). Furthermore, in the above embodiments, a sumand/or difference is used, however, as disclosed in the Japanese PatentApplication Laid-open No. Hei5-181896, by using a selecting format ofsignals, the present invention can be implemented equally.

Thus, according to the present invention, since the 2^(N)-2^(N) DCT and2−2^(N−1)−2^(N) DCT device are so configured that a part of the fixedcoefficient multiplying circuit used in the 2^(N)-2^(N) DCT circuit canbe used, by being switched, as the fixed coefficient multiplying circuitrequired in the 2−2^(N−1)−2^(N) DCT, a high-speed calculatingcharacteristic obtained through the pipeline processing type arithmeticoperation in the 2^(N)-2^(N) DCT can be maintained in the2−2^(N−1)−2^(N) DCT and the high-speed calculating characteristic can bestill maintained in even miniaturized 2^(N)-2^(N) DCT devices and2−2^(N−1)2^(N) DCT devices. The same effects as above can be achieved inthe 2^(N)-2^(N) IDCT devices and 2−2^(N)−2^(N) IDCT devices according tothe present invention.

What is claimed is:
 1. A method for compressing image signalscomprising: a selection process of selecting 2^(N) pieces of pictureelement data fj (0≦j≦2^(N)−1) contained in one line or one stringconstituting a block of 2^(N)×2^(N) (N being a natural number) pieces ofpicture element data forming image data, for each of fixed coefficientsPk given in equation (1) and equation (2) and determined in accordancewith a discrete cosine transformation rule; a multiplication process ofmultiplying each piece of selected said picture element data by each ofcorresponding said fixed coefficients Pk to obtain products; anaddition/subtraction process of performing adding operations and/orsubtracting operations between products obtained by said multiplicationprocess and determined in accordance with said discrete cosinetransformation rule; and an output process of outputting a valueobtained by said addition/subtraction process as transformationcoefficient data Fj for each line or each string constituting said blockof 2^(N)×2^(N) picture element data; wherein, in said selection process,first set and second set of picture element data composed of 2^(N)pieces of picture element data contained in one line or one stringconstituting said block of 2^(N)×2^(N) pieces of picture element dataare selected for each of fixed coefficients, out of said fixedcoefficients Pk, with k in odd-numbered positions in said equation (1)and said equation (2), in a predetermined order, and wherein, in saidmultiplication process, said first set and said second set of pictureelement data selected for each of said fixed coefficients with k inodd-numbered positions in said equation (1) and said equation (2) aremultiplied by each of said fixed coefficients with k in odd-numberedpositions in said equation (1) and said equation (2) to obtain saidproduct; $\begin{matrix}{P_{k} = {\cos \quad \left( \frac{\left( {N - 1 - k} \right)\pi}{2^{N + 1}} \right)}} & (1)\end{matrix}$

 0≦k≦2^(N−1)−2 where k=2^(N−1)−1 is excluded; $\begin{matrix}{P_{k} = \frac{1}{\sqrt{2}}} & (2)\end{matrix}$

(k=2^(N−1)−1).
 2. The method for compressing image data according toclaim 1, wherein a sum of 2^(N) pieces of picture element data having“j” data contained in said picture element data fj, one beinglower-numbered data and the other being the next lower-numbered data,and thereafter in the same manner, is selected as said first set ofpicture element data to be selected in said selection process andwherein a difference between 2^(N) pieces of picture element data having“j” data contained in said picture element data fj, one beinglower-numbered data and the other being the next lower-numbered data,and thereafter in the same manner, is selected as said second set ofpicture element data to be selected in said selection process.
 3. Amethod for decompressing image signals comprising: a selection processof selecting 2^(N) pieces of transformation coefficient data Fj(0≦j≦2^(N)−1) contained in one line or one string constituting a blockof 2^(N)×2^(N) (N being a natural number) pieces of transformationcoefficient data block forming transformation coefficient datatransmitted after being transformed by a discrete cosine transformationmethod, for each of fixed coefficients Pk given in equation (3) andequation (4) and determined in accordance with a discrete cosinetransformation rule; a multiplication process of multiplying each ofsaid selected transformation coefficient data by each of saidcorresponding fixed coefficients Pk to obtain products; anaddition/subtraction process of performing adding operations and/orsubtracting operations between products obtained by said multiplicationprocess which is determined in accordance with said discrete cosinetransformation rule; an output process of outputting a value obtained bysaid addition/subtraction process as picture element data fj for eachline or each string constituting said block of 2^(N)×2^(N) pictureelement data; wherein, in said selection process, first set and secondset of transformation coefficient data composed of 2^(N) pieces oftransformation coefficient data contained in one line or one stringconstituting said block of 2^(N)×2^(N) pieces of transformationcoefficient data are selected for each of fixed coefficients, out ofsaid fixed coefficients Pk, with k in odd-numbered positions in saidequation (3) and said equation (4), in a predetermined order, andwherein, in said multiplication process, each of said first set and saidsecond set of transformation coefficient data selected for each of saidfixed coefficients with k in odd-numbered positions in said equation (3)and said equation (4) is multiplied by each of said fixed coefficientswith k in odd-numbered positions in said equation (3) and said equation(4) to obtain said product; $\begin{matrix}{P_{k} = {\cos \left( \frac{\left( {N - 1 - k} \right)\pi}{2^{N + 1}} \right)}} & (3)\end{matrix}$

 0≦k≦2^(N−1)−2 where k=2^(N−1)−1 is excluded; $\begin{matrix}{P_{k} = \frac{1}{\sqrt{2}}} & (4)\end{matrix}$

(k=2^(N−1)−1).
 4. The method for decompressing image signals accordingto claim 3, wherein said first set of transformation coefficient data isa sum of transformation coefficient data composed of one data selectedfrom a first transformation data set containing “j” data constitutingfirst half of said 2^(N) pieces of transformation coefficient data Fjand containing 2^(N−1) pieces of transformation coefficient data andtransformation coefficient data composed of one data selected from asecond transformation data set containing “j” data constituting secondhalf of said 2^(N) pieces of transformation coefficient data Fj andcontaining 2^(N−1) pieces of transformation coefficient data and whereinsaid second set of transformation data is a difference betweentransformation coefficient data composed of one data selected from saidfirst transformation data set and transformation coefficient datacomposed of one data selected from said second transformation data set.5. A method for compressing image signals comprising: a selectionprocess of selecting 2^(N) pieces of picture element data fj(0≦j≦2^(N)−1) contained in one line or one string constituting a blockof 2^(N)×2^(N) (N being a natural number) pieces of picture element datablock forming image data, for each of fixed coefficients Pk given inequation (5) and equation (6) and determined in accordance with adiscrete cosine transformation rule; a multiplication process ofmultiplying each of said selected picture element data by each of saidcorresponding fixed coefficients Pk to obtain products; anaddition/subtraction process of performing adding operations and/orsubtracting operations between products obtained by said multiplicationprocess and determined in accordance with said discrete cosinetransformation rule; and an output process of outputting a valueobtained by said addition/subtraction process as transformationcoefficient data Fj for each line or each string constituting said blockof 2^(N)×2^(N) picture element data; wherein, in said selection process,in the case of 2^(N)-2^(N) discrete cosine transformation, 2^(N) piecesof picture element data are selected from 2^(N) pieces of pictureelement data contained in one line or one string constituting said blockof 2^(N)×2^(N) picture element data for each of said fixed coefficientsPk determined by said 2^(N)-2^(N) discrete cosine transformation in apredetermined order and wherein, in said selection process, in the caseof 2−2^(N−1)−2^(N) discrete cosine transformation, each of first set andsecond set of picture element data each being composed of 2^(N) piecesof picture element data to be multiplied by each of fixed coefficients,out of said fixed coefficients Pk, with k in odd-numbered positions insaid equation (5) and said equation (6), is selected from 2^(N) piecesof picture element data contained in one line or one string constitutingsaid block of 2^(N)×2^(N) pieces of picture element data in apredetermined order, wherein, in said multiplication process, in thecase of said 2^(N)-2^(N) discrete cosine transformation, each of said2^(N) pieces of picture element data selected in said selection processis multiplied by each of said corresponding fixed coefficients out ofsaid fixed coefficients Pk to obtain products and wherein, in the caseof said 2−2^(N−1)−2^(N) discrete cosine transformation, each of saidfirst set and second set of picture element data selected based oncorresponding fixed coefficient, out of said fixed coefficient Pk, withk in odd-numbered positions in said equation (5) and said equation (6)is multiplied by said fixed coefficients, out of said fixed coefficientsPk, with k in odd-numbered positions in said equation (5) and saidequation (6); and wherein, in said addition/subtraction process, in thecase of said 2^(N)-2^(N) discrete cosine transformation, said addingoperations and/or said subtracting operations are performed betweenproducts obtained by said multiplication process and determined inaccordance with said 2^(N)-2^(N) discrete cosine transformation andwherein, in the case of said 2−2^(N−1)−2^(N) discrete cosinetransformation, said adding operations and/or said subtractingoperations are performed between products obtained by saidmultiplication process and determined in accordance with said2−2^(N−1)−2^(N) discrete cosine transformation rule; $\begin{matrix}{P_{k} = {\cos \left( \frac{\left( {N - 1 - k} \right)\pi}{2^{N + 1}} \right)}} & (5)\end{matrix}$

 0≦k≦2^(N−1)−2 where k=2^(N−1)−1 is excluded; $\begin{matrix}{P_{k} = \frac{1}{\sqrt{2}}} & (6)\end{matrix}$

(k=2^(N−1)−1).
 6. The method for compressing image signals according toclaim 5, wherein said picture element data to be selected in said blockof 2^(N)-2^(N) discrete cosine transformation includes said first set ofpicture element data composed of said 2^(N) pieces of picture elementdata contained in one line or one string constituting said block of2^(N)×2^(N) pieces of picture element data to be multiplied by each ofsaid fixed coefficients, out of said fixed coefficients Pk, with k inodd-numbered positions in said equation (5) and equation (6) and saidsecond set of picture element data composed of said 2^(N) pieces ofpicture element data to be multiplied by each of fixed coefficients, outof said fixed coefficients Pk, with k in odd-numbered positions in saidequation (5) and equation (6).
 7. The method for compressing imagesignals according to claim 5 or claim 6, wherein said picture elementdata selected in said selection process is a sum and difference betweenpicture element data constituting a predetermined pair of pictureelement data.
 8. The method for compressing image signals according toclaim 7, wherein said picture element data constituting saidpredetermined pair of picture element data, in the case of said2−2^(N−1)−2^(N) discrete cosine transformation, are 2^(N) pieces ofpicture element data having “j” data contained said picture element datafj, one being lower-numbered data and the other being the nextlower-numbered data.
 9. The method for compressing image signalsaccording to claim 7, wherein said picture element data constitutingsaid predetermined pair of picture element data, in the case of said2^(N)-2^(N) discrete cosine transformation, are picture element datacomposed of one data selected from said first transformation data setcontaining “j” data which constitutes first half of said 2^(N) pieces ofpicture element data Fj and containing 2^(N−1) pieces of picture elementdata and picture element data composed of one data selected from saidsecond picture element data set containing “j” data which constitutessecond half of said 2^(N) pieces of picture element data fj andcontaining 2^(N−1) pieces of picture element data.
 10. A method fordecompressing image signals comprising: a selection process of selecting2^(N) pieces of transformation coefficient data Fj (0≦j≦2^(N)−1)contained in one line or one string constituting a block of 2^(N)×2^(N)(N being a natural number) pieces of transformation coefficient datablock forming transformation coefficient data transmitted after beingtransformed by a discrete cosine transformation method, for each offixed coefficients Pk given in equation (7) and equation (8) anddetermined in accordance with a discrete cosine transformation rule; amultiplication process of multiplying each of said selectedtransformation coefficient data by each of said corresponding fixedcoefficients Pk to obtain products; an addition/subtraction process ofperforming adding operations and/or subtracting operations betweenproducts obtained by said multiplication process and determined inaccordance with said discrete cosine transformation rule; and an outputprocess of outputting a value obtained by said addition/subtractionprocess as picture element data fj for each line or each stringconstituting said block of 2^(N)×2^(N) transformation coefficient data;wherein, in said selection process, in the case of 2^(N)-2^(N) inversediscrete cosine transformation, each of said 2^(N) pieces oftransformation coefficient data is selected from 2^(N) pieces oftransformation coefficient data contained in one line or one stringconstituting said block of 2^(N)×2^(N) transformation coefficient datafor each of said fixed coefficients Pk determined by said 2^(N)-2^(N)inverse discrete cosine transformation method in a predetermined order,and wherein, in said selection process, in the case of 2−2^(N−1)−2^(N)inverse discrete cosine transformation, first set and second set oftransformation coefficient data each being composed of 2^(N) pieces oftransformation coefficient data contained in one line or one stringconstituting said block of 2^(N)×2^(N) pieces of transformationcoefficient data are selected for each of fixed coefficients, out ofsaid fixed coefficients Pk, with k in odd-numbered positions in saidequation (7) and said equation (8) in a predetermined order, wherein, insaid multiplication process, in the case of said 2^(N)-2^(N) inversediscrete cosine transformation, each of said 2^(N) pieces of pictureelement data selected in said selection process is multiplied by each ofcorresponding fixed coefficients out of said fixed coefficients Pk toobtain products and wherein, in the case of said 2−2^(N−1)−2^(N) inversediscrete cosine transformation, each of said first set and second set oftransformation coefficient data selected based on each of correspondingfixed coefficients, out of said fixed coefficients Pk, with k inodd-numbered positions in said equation (7) and said equation (8) ismultiplied by each of said fixed coefficients, out of said fixedcoefficients Pk, with k in odd-numbered positions in said equation (7)and said equation (8) to obtain products, wherein, in saidaddition/subtraction process, in the case of said 2^(N)-2^(N) inversediscrete cosine transformation, said adding operations and/orsubtracting operations are performed between products obtained by saidmultiplication process and determined in accordance with said2^(N)-2^(N) discrete cosine transformation rule and wherein, in the caseof said 2−2^(N−1)−2^(N) inverse discrete cosine transformation, saidadding operations and/or said subtracting operations are performedbetween products obtained by said multiplication process and determinedin accordance with said 2−2^(N−1)−2^(N) discrete cosine transformationrule; $\begin{matrix}{P_{k} = {\cos \left( \frac{\left( {N - 1 - k} \right)\pi}{2^{N + 1}} \right)}} & (7)\end{matrix}$

 0≦k≦2^(N−1)−2 where k=2^(N−1)−1 is excluded; $\begin{matrix}{P_{k} = \frac{1}{\sqrt{2}}} & (8)\end{matrix}$

(k=2^(N−1)−1).
 11. The method for decompressing image signals accordingto claim 10, wherein said transformation coefficient data to be selectedin said 2^(N)-2^(N) inverse discrete cosine transformation includes saidfirst set of transformation coefficient data composed of said 2^(N)pieces of transformation coefficient data contained in one line or onestring constituting said block of 2^(N)×2^(N) pieces of transformationcoefficient data to be multiplied by each of said fixed coefficients,out of said fixed coefficients Pk, with k in odd-numbered positions insaid equation (7) and said equation (8) and said second set oftransformation coefficient data composed of said 2^(N) pieces oftransformation coefficient data to be multiplied by each of fixedcoefficients, out of said fixed coefficients Pk, with k in odd-numberedpositions in said equation (7) and said equation (8).
 12. A device forcompressing image signals comprising: a selection circuit for selecting2^(N) pieces of picture element data fj (0≦j≦2^(N)−1) contained in oneline or one string constituting a block of 2^(N)×2^(N) (N being anatural number) pieces of picture element data block forming image data,for each of fixed coefficients Pk given in equation (9) and equation(10) and determined in accordance with a discrete cosine transformationrule; a multiplication circuit for multiplying each of said selectedpicture element data by each of said corresponding fixed coefficients Pkto obtain products; an addition/subtraction circuit for performingadding operations and/or subtracting operations between productsobtained by said multiplication process and determined in accordancewith said discrete cosine transformation rule; and an output circuit foroutputting a value obtained by said adding operations and/or subtractingoperations as transformation coefficient data Fj for each line or eachstring constituting said block of 2^(N)×2^(N) picture element data;wherein said selection circuit is that each of said first set and secondset of picture element data composed of 2^(N) pieces of picture elementdata contained in one line or one string constituting said block of2^(N)×2^(N) pieces of picture element data is selected for each of fixedcoefficients, out of said fixed coefficients Pk, with k in odd-numberedpositions in said equation (9) and said equation (10), in apredetermined order, and wherein, in said multiplication process, eachof said first set and second set of picture element data selected foreach of said fixed coefficients with k in odd-numbered positions in saidequation (9) and said equation (10) is multiplied by said fixedcoefficient with k in odd-numbered positions in said equation (9) andsaid equation (10) to obtain said product; $\begin{matrix}{P_{k} = {\cos \left( \frac{\left( {N - 1 - k} \right)\pi}{2^{N + 1}} \right)}} & (9)\end{matrix}$

 0≦k≦2^(N−1)−2 where k=2^(N−1)−1 is excluded; $\begin{matrix}{P_{k} = \frac{1}{\sqrt{2}}} & (10)\end{matrix}$

(k=2^(N−1)−1).
 13. The device for compressing image signals according toclaim 12, wherein a sum of 2^(N) pieces of picture element data having“j” data contained in said picture element data fj, one beinglower-numbered data and the other being the next lower-numbered data,and thereafter in the same manner, is selected by said selection circuitas said first set of picture element data and wherein a differencebetween 2^(N) pieces of picture element data having “j” data containedin said picture element data fj, one being lower-numbered data and theother being the next lower-numbered data and thereafter in the samemanner, is selected by said selection circuit as said second set ofpicture element.
 14. A device for decompressing image signalscomprising: a selection circuit for selecting 2^(N) pieces oftransformation coefficient data Fj (0≦j≦2^(N)−1) contained in one lineor one string constituting a block of 2^(N)×2^(N) (N being a naturalnumber) pieces of transformation coefficient data block formingtransformation coefficient data transmitted after being transformed by adiscrete cosine transformation method, for each of fixed coefficients Pkgiven in equation (11) and equation (12) and determined in accordancewith a discrete cosine transformation rule; a multiplication circuit formultiplying each of said selected transformation coefficient data byeach of said corresponding fixed coefficient Pk to obtain products; anaddition/subtraction circuit for performing adding operations and/orsubtracting operations between products obtained by said multiplicationprocess which is determined in accordance with said discrete cosinetransformation rule; and an output circuit for outputting a valueobtained by said adding operations and/or subtracting operations aspicture element data fj for each line or each string constituting saidblock of 2^(N)×2^(N) picture element data; wherein said selectioncircuit is that each of first set and second set of transformationcoefficient data composed of 2^(N) pieces of transformation coefficientdata contained in one line or one string constituting said block of2^(N)×2^(N) pieces of transformation coefficient data block is selectedfor each of fixed coefficients, out of said fixed coefficients Pk, withk in odd-numbered positions in said equation (11) and said equation(12), in a predetermined order, and wherein said multiplication circuitis that each of said first set and second set of transformationcoefficient data selected for each of said fixed coefficients with k inodd-numbered positions in said equation (11) and said equation (12) ismultiplied by each of said fixed coefficients with k in odd-numberedpositions in said equation (11) and said equation (12) to obtain saidproduct; $\begin{matrix}{P_{k} = {\cos \left( \frac{\left( {N - 1 - k} \right)\pi}{2^{N + 1}} \right)}} & (11)\end{matrix}$

 0≦k≦2^(N−1)−2 where k=2^(N−1)−1 is excluded; $\begin{matrix}{P_{k} = \frac{1}{\sqrt{2}}} & (12)\end{matrix}$

(k=2^(N−1)−1).
 15. The device for decompressing image signals accordingto claim 14, wherein said selection circuit, selects, as said first setof transformation coefficient data, a sum of transformation coefficientdata composed of one data selected from a first transformation data setcontaining “j” data which constitutes first half of said 2^(N) pieces oftransformation coefficient data Fj and containing 2^(N−1) pieces oftransformation coefficient data and transformation coefficient datacomposed of one data selected from a second transformation data setcontaining “j” data which constitutes second half of said 2^(N) piecesof transformation coefficient data Fj and containing 2^(N−1) pieces oftransformation coefficient data and wherein said selection circuit,selects, as said second set of transformation data, a difference betweentransformation coefficient data composed of one data selected from saidfirst transformation data set and transformation coefficient datacomposed of one data selected from said second transformation data set.16. A device for compressing image signals comprising: a selectioncircuit for selecting 2^(N) pieces of picture element data fj(0≦j≦2^(N)−1) contained in one line or one string constituting a blockof 2^(N)×2^(N) (N being a natural number) pieces of picture element datablock forming image data, for each of fixed coefficients Pk given inequation (13) and equation (14) and determined in accordance with adiscrete cosine transformation rule; a multiplication circuit formultiplying each of said selected picture element data by each of saidcorresponding fixed coefficients Pk to obtain products; anaddition/subtraction circuit for performing adding operations and/orsubtracting operations between products obtained by said multiplicationcircuit and determined in accordance with said discrete cosinetransformation rule; and an output circuit for outputting a valueobtained by said adding operations and/or subtracting operations astransformation coefficient data Fj for each line or each stringconstituting said block of 2^(N)×2^(N) picture element data; whereinsaid selection circuit, in the case of 2^(N)-2^(N) discrete cosinetransformation, selects 2^(N) pieces of picture element data from 2^(N)pieces of picture element data contained in one line or one stringconstituting said block of 2^(N)×2^(N) picture element data block foreach of said fixed coefficients Pk determined by said 2^(N)-2^(N)discrete cosine transformation method in a predetermined order andwherein said selection circuit, in the case of 2−2^(N−1)−2^(N) discretecosine transformation, selects each of first set and second set ofpicture element data each being composed of 2^(N) pieces of pictureelement data to be multiplied by each of fixed coefficients, out of saidfixed coefficients Pk, with k in odd-numbered positions in said equation(13) and said equation (14), from 2^(N) pieces of picture element datacontained in one line or one string constituting said block of2^(N)×2^(N) pieces of picture element data block in a predeterminedorder, wherein said multiplication circuit, in the case of said2^(N)-2^(N) discrete cosine transformation, multiplies each of said2^(N) pieces of picture element data selected by said selection circuitby each of corresponding fixed coefficients out of said fixedcoefficients Pk to obtain products and wherein said multiplicationcircuit, in the case of said 2−2^(N−1)−2^(N) discrete cosinetransformation, multiplies each of said first set and said second set ofpicture element data selected based on each of corresponding fixedcoefficients, out of said fixed coefficients Pk, with k in odd-numberedpositions in said equation (13) and said equation (14) by each of saidfixed coefficients, out of said fixed coefficients Pk, with k inodd-numbered positions in said equation (13) and said equation (14), andwherein said addition/subtraction circuit, in the case of said2^(N)-2^(N) discrete cosine transformation, performs said addingoperations and/or said subtracting operations between products obtainedby said multiplication process and determined in accordance with said2^(N)-2^(N) discrete cosine transformation and wherein saidaddition/subtraction circuit, in the case of said 2−2^(N−1)−2^(N)discrete cosine transformation, performs said adding operations and/orsaid subtracting operations between products obtained by saidmultiplication process and determined in accordance with said2−2^(N−1)−2^(N) discrete cosine transformation rule; $\begin{matrix}{P_{k} = {\cos \left( \frac{\left( {N - 1 - k} \right)\pi}{2^{N + 1}} \right)}} & (13)\end{matrix}$

 0≦k≦2^(N−1)−2 where k=2^(N−1)−1 is excluded; $\begin{matrix}{P_{k} = \frac{1}{\sqrt{2}}} & (14)\end{matrix}$

(k=2^(N−1)−1).
 17. The device for compressing image signals according toclaim 16, wherein said picture element data to be selected in said2^(N)-2^(N) discrete cosine transformation includes said first set ofpicture element data composed of said 2^(N) pieces of picture elementdata contained in one line or one string constituting said block of2^(N)×2^(N) pieces of picture element data block to be multiplied byeach of said fixed coefficients, out of said fixed coefficients Pk, withk in odd-numbered in said equation (13) and said equation (14) and saidsecond set of picture element data composed of said 2^(N) pieces ofpicture element data to be multiplied by each of fixed coefficients, outof said fixed coefficients Pk, with k in odd-numbered positions in saidequation (13) and said equation (14).
 18. The device for compressingimage signals according to claim 16, wherein said selection circuit,selects, as said picture element data, a sum and difference betweenpicture element data constituting a predetermined pair of pictureelements.
 19. The device for compressing image signals according toclaim 18, wherein said selection circuit selects, as said pictureelement data constituting said predetermined pair of picture elementdata, in the case of said 2−2^(N−1)−2^(N) discrete cosinetransformation, 2^(N) pieces of picture element data having “j” datacontained in said picture element data fj, one being lower-numbered dataand the other being the next lower-numbered data.
 20. The device forcompressing image signals according to claim 18, wherein said selectioncircuit selects, as said picture element data constituting saidpredetermined pair of picture element data, in the case of said2^(N)-2^(N) discrete cosine transformation, picture element datacomposed of one data selected from said first transformation data setcontaining “j” data constituting first half of said 2^(N) pieces ofpicture element data Fj and containing 2^(N−1) pieces of picture elementdata and picture element data composed of one data selected from saidsecond picture element data set containing “j” data constituting secondhalf of said 2^(N) pieces of picture element data fj and containing2^(N−1) pieces of picture element data.
 21. A device for decompressingimage signals comprising: a selection circuit for selecting 2^(N) piecesof transformation coefficient data Fj (0≦j≦2^(N)−1) contained in oneline or one string constituting a block of 2^(N)×2^(N) (N being anatural number) pieces of transformation coefficient data block formingtransformation coefficient data transmitted after being transformed by adiscrete cosine transformation method, for each of fixed coefficients Pkgiven in equation (15) and equation (16) and determined in accordancewith a discrete cosine transformation rule; a multiplication circuit formultiplying each of said selected transformation coefficient data byeach of said corresponding fixed coefficients Pk to obtain products; anaddition/subtraction circuit for performing adding operations and/orsubtracting operations between products obtained by said multiplicationcircuit and determined in accordance with said discrete cosinetransformation rule; and an output circuit for outputting a valueobtained by said adding operations and/or subtracting operations aspicture element data fj for each line or each string constituting saidblock of 2^(N)×2^(N) transformation coefficient data; wherein saidselection circuit, in the case of 2^(N)-2^(N) inverse discrete cosinetransformation, selects 2^(N) pieces of transformation coefficient datafrom 2^(N) pieces of transformation coefficient data contained in oneline or one string constituting said block of 2^(N)×2^(N) transformationcoefficient data for each of said fixed coefficients Pk determined bysaid 2^(N)-2^(N) inverse discrete cosine transformation rule in apredetermined order, and wherein said selection circuit, in the case of2−2^(N−1)−2^(N) inverse discrete cosine transformation, selects firstset and second set of transformation coefficient data each beingcomposed of 2^(N) pieces of transformation coefficient data contained inone line or one string constituting said block of 2^(N)×2^(N) pieces oftransformation coefficient data for each of fixed coefficients, out ofsaid fixed coefficients Pk, with k in odd-numbered positions in saidequation (15) and said equation (16) in a predetermined order, wherein,said multiplication circuit, in the case of said 2^(N)-2^(N) inversediscrete cosine transformation, multiplies each of 2^(N) pieces ofpicture element data selected in said selection process by each ofcorresponding fixed coefficients, out of said fixed coefficients Pk, toobtain products and wherein said multiplication circuit, in the case ofsaid 2−2^(N−1)−2^(N) inverse discrete cosine transformation, multiplieseach of said first set and said second set of transformation coefficientdata selected based on each of corresponding fixed coefficients, out ofsaid fixed coefficients Pk, with k in odd-numbered positions in saidequation (15) and said equation (16) by each of said fixed coefficients,out of said fixed coefficients Pk, with k in odd-numbered positions insaid equation (15) and said equation (16) to obtain products, wherein,said addition/subtraction circuit, in the case of said 2^(N)-2^(N)inverse discrete cosine transformation, performs said adding operationsand/or said subtracting operations between products obtained by saidmultiplication circuit and determined in accordance with said2^(N)-2^(N) discrete cosine transformation and wherein, saidaddition/subtraction circuit, in the case of said 2−2^(N−1)−2^(N)inverse discrete cosine transformation, performs said adding operationsand subtracting/or operations between products obtained by saidmultiplication process and determined in accordance with said2−2^(N−1)−2^(N) discrete cosine transformation; $\begin{matrix}{P_{k} = {\cos \left( \frac{\left( {N - 1 - k} \right)\pi}{2^{N + 1}} \right)}} & (15)\end{matrix}$

 0≦k≦2^(N−1)−1 where k=2^(N−1)−1 is excluded; $\begin{matrix}{P_{k} = \frac{1}{\sqrt{2}}} & (16)\end{matrix}$

(k=2^(N−1)−1).
 22. The device for decompressing image signals accordingto claim 21, wherein said selection circuit, in said 2^(N)-2^(N) inversediscrete cosine transformation, as said transformation coefficient data,selects said first set of transformation coefficient data composed ofsaid 2^(N) pieces of transformation coefficient data contained in oneline or one string constituting said block of 2^(N)×2^(N) pieces oftransformation coefficient data to be multiplied by each of said fixedcoefficients, out of said fixed coefficients Pk, with k in odd-numberedpositions in said equation (15) and said equation (16) and said secondset of transformation coefficient data composed of said 2^(N) pieces oftransformation coefficient data to be multiplied by each of fixedcoefficients, out of said fixed coefficients Pk, with k in even-numberedpositions in said equation (15) and said equation (16).